ECC Engine Error Vector Correction for Semiconductor Memory Yield
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Solution Overview
Problem
The increasing memory capacity of semiconductor memory devices leads to a higher incidence of defective and weak memory cells, which can result in data storage errors, and existing error correction methods are insufficient to effectively address the growing number of single bit errors, hindering manufacturing yield improvements.
Innovation Solution
The implementation of an error correction circuit using an Error Correction Code (ECC) engine within semiconductor memory devices, which includes a register for storing error vectors, performs ECC decoding, and generates syndrome data to correct errors, enabling the detection and correction of single bit errors through a code validation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased to provide larger storage, then storage capacity is improved, but the incidence of defective and weak memory cells increases leading to more data storage errors
Solution Approach 1:
The patent applies preliminary action by performing ECC decoding and error detection before data is fully written to or read from the increased-capacity memory. The error correction circuit proactively identifies and corrects potential errors in defective cells before they propagate, allowing the system to safely utilize larger memory capacity while maintaining data integrity through pre-emptive error handling
2Device complexity
If existing error correction methods are used without enhancement, then device complexity is maintained, but the ability to correct single bit errors is insufficient leading to reduced manufacturing yield
Solution Approach 1:
The patent implements feedback by using syndrome data generated from parity bits to automatically identify and correct error patterns in stored data. The error correction circuit continuously monitors data integrity through syndrome calculation and uses this feedback information to selectively correct single bit errors, thereby improving manufacturing yield without requiring proportionally complex circuitry
Solution Approach 2:
The error correction circuit performs self-service by autonomously detecting and correcting its own errors using embedded parity bits and syndrome data. The system does not require external intervention for error correction, as the ECC engine automatically generates correction signals based on the syndrome data and applies them to fix single bit errors, improving reliability while maintaining acceptable device complexity
Data Source
AI summary
A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.