ECC Engine Error Information Generation Circuit
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Solution Overview
Problem
As memory device capacity increases, it becomes challenging to produce memory devices with no defective memory cells, leading to the need for error correction and redundancy to address these defects.
Innovation Solution
A memory system that includes a memory core, an error correction code (ECC) engine for detecting errors, and an error information generation circuit that outputs error information to a memory controller, indicating whether errors are correctable or uncorrectable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent segments error handling into multiple categories (correctable errors, uncorrectable errors, and error patterns) and processes each segment differently. The ECC engine divides error detection into syndromes that can identify specific error types, allowing targeted correction strategies for different error segments rather than treating all errors uniformly.
Solution Approach 2:
The patent performs preliminary error detection and classification before data transmission or processing. The ECC engine calculates syndromes and identifies error patterns in advance, determining whether errors are correctable or uncorrectable before the data is used, allowing the system to prepare appropriate error handling measures proactively.
2Reliability
If error correction is implemented, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and separates error information from data bits, using dedicated syndrome bits to carry error detection and classification information. The ECC code structure separates data bits from syndrome bits, allowing error handling information to be processed independently from the actual data, simplifying the overall error correction architecture.
Solution Approach 2:
The patent introduces syndrome bits as an intermediary between the data and the error correction mechanism. These syndrome bits serve as mediators that carry error detection information without requiring direct complex interaction between data bits and correction logic, simplifying the error handling process.
3Reliability
If accurate error information is reported to memory controller, then system reliability is improved, but communication overhead increases
Solution Approach 1:
The patent applies partial action by reporting only the necessary error information to the memory controller rather than transmitting complete error details. The system transmits condensed error flags indicating correctable or uncorrectable errors, providing sufficient information for reliability monitoring without the overhead of detailed error data transmission.
Data Source
AI summary
A memory may include a memory core; an error correction code (ECC) engine that reads data and an error correction code from the memory core and detects an error in the data using the data and the error correction code; and an error information generation circuit that generates error information to be output to an outside of the memory in response to an error detection result of the ECC engine, the error information including the number of errors being less than the number of errors included in the error detection result.