Memory ECC Redundancy for Row-Column Intersection Error Floors
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Solution Overview
Problem
Memory devices face challenges in error correction, particularly when decoding data with block-wise concatenated codes, as they often reach an error floor where conventional methods fail to correct errors located at the intersections of column and row codewords, leading to decode failures.
Innovation Solution
Incorporating parity data for cross-over bits at the intersections of column and row codewords, which are created through an XOR operation, to enhance error correction capabilities, allowing for increased correction of errors beyond the initial code's capacity and potentially eliminating the need for an outer code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC decoding methods are used for block-wise concatenated codes, then decoding complexity is reduced, but error correction capability deteriorates due to error floors at codeword intersections
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing syndrome values for all possible error patterns at codeword intersections during the encoding phase. These pre-computed syndromes are stored in lookup tables, allowing the decoder to quickly identify and correct errors without performing complex real-time calculations, thus resolving the contradiction between reliability and decoding complexity
Solution Approach 2:
The patent introduces a new dimension to error correction by adding cross-over parity bits that specifically protect intersection points between row and column codewords. This dimensional extension creates an additional layer of redundancy that targets the specific problem area (intersections) without requiring complete redesign of the entire decoding mechanism, thereby improving reliability while maintaining acceptable complexity
2Reliability
If parity data for cross-over bits is incorporated, then error correction capability increases, but memory overhead increases
Solution Approach 1:
The patent applies local quality by providing enhanced protection only at specific locations (codeword intersections) rather than uniformly across all data bits. Cross-over parity bits are generated only for intersection points where row and column codewords meet, concentrating redundancy resources where errors are most likely to occur and persist, thus improving error correction capability while minimizing overall memory overhead
Solution Approach 2:
The patent uses partial action by implementing error correction enhancement only for the specific subset of bits located at codeword intersections, rather than applying full redundancy to all data. This selective approach provides sufficient correction capability for the most problematic error locations without the excessive overhead of universal redundancy, resolving the contradiction between reliability improvement and memory overhead
Data Source
AI summary
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.