ECC Error Trap Registers for Detailed Failure Debugging
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Solution Overview
Problem
Current Error Correction Code (ECC) systems in symmetrical computer systems have limitations in debugging, such as only trapping the first or last error, counting total errors without control over which error is counted, and lacking information on specific failures, which hinders detailed debugging and fault analysis.
Innovation Solution
The introduction of new trap registers and counters allows for customizable trapping conditions, enabling the detection of bit errors, accumulation of error information, comparison of ECC syndromes, and specific error counting, as well as the ability to stop the system for debugging purposes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If trap registers are used to capture error information, then debugging capability is improved, but chip space is consumed
Solution Approach 1:
The trap register system is designed to serve multiple functions: it can trap correctable errors, uncorrectable errors, or both types simultaneously based on configuration; it can trap the first occurrence, last occurrence, or all occurrences of errors; and it can provide different levels of error information. This multi-functionality maximizes the utility of the trap registers while minimizing the number of separate trapping mechanisms needed, thereby optimizing chip space usage.
2Device complexity
If only total error counting is implemented, then device complexity is reduced, but debugging information completeness is insufficient
Solution Approach 1:
The error counting functionality is segmented into multiple independent counters: a first counter for correctable errors and a second counter for uncorrectable errors. This segmentation allows each counter to track specific error types independently, providing comprehensive error information without requiring a single complex counting mechanism. The segmented approach enables selective monitoring of different error categories while maintaining relatively simple individual counter designs.
3Loss of information
If trap registers capture all error types, then error information completeness is improved, but trap register utilization efficiency decreases
Solution Approach 1:
The trap register system incorporates dynamic configuration capabilities where the trapping behavior can be adjusted based on system needs. The trap registers can be configured to trap only correctable errors, only uncorrectable errors, or both types, and can be set to capture the first occurrence, last occurrence, or all occurrences of errors. This dynamic adaptability allows the system to optimize trap register utilization for specific debugging scenarios while maintaining complete error information capture capability when needed.
Data Source
AI summary
A method of error correction code (ECC) debugging for a system comprising, receiving data having an ECC, determining whether a data error has occurred, generating a syndrome of an error result, decoding flipped data bits, processing the received data and the decoded flipped bits to correct the data, outputting corrected data having an ECC, receiving a trap update signal, and saving the decoded flipped data bits responsive to receiving the trap update signal.