ECC Checker Logic Fault Injection for ADAS Memory Diagnostics

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Solution Overview

Problem

Existing ECC syndrome generation and checking logic in ADAS/ADS systems is susceptible to random faults, which can lead to false memory faults or missed actual faults, potentially causing system failures during mission mode in safety-critical systems like vehicle automated driving systems.

Innovation Solution

A test system and method are provided to test ECC checker logic for faults before workload processing, using fault injection logic to inject a test bit pattern, alter the ECC syndrome, and compare the generated fault signature with an expected signature to detect any discrepancies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC syndrome generation and checking logic is used to detect bit faults in memory, then memory fault detection capability is improved, but the logic itself becomes susceptible to random faults that can cause false memory faults or missed actual faults

Engineering Contradiction:

Improvememory fault detection capabilityVSAvoidrandom faults in ECC logic

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements preliminary testing of the ECC logic at power-on time before the system enters mission mode. A test mode is activated that injects known fault conditions into the ECC checker logic and verifies whether the logic correctly detects these injected faults. This preliminary action ensures the ECC logic is functional before actual memory operations begin, preventing undetected faults from causing system failures during mission mode.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If ECC testing is performed during power-on time before workload, then system reliability is improved by detecting faults early, but testing time must be allocated within the power-on sequence which may extend the initialization duration

Engineering Contradiction:

Improvesystem reliabilityVSAvoidpower-on initialization duration

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic testing by repeating the ECC logic test multiple times during the power-on sequence. Each test iteration follows a consistent periodic pattern: activate test mode, inject fault conditions, verify detection, and repeat. This periodic action ensures thorough testing while maintaining a structured timeline that fits within the power-on initialization window, balancing reliability verification with initialization time constraints.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS12518846B2Systems and methods for testing error correction code (ECC) logic of automotive safety systems for faults

Publication Date: 2026.01.06 QUALCOMM INC

AI summary

An error correction code (ECC) test system and method are provided that test ECC logic for faults, preferably at power on before a workload is being processed. If the ECC logic fails the test, preferably an interrupt is issued indicating that the ECC logic is faulty and the corresponding ECC fault signature is reported in a status register of the system as part of a consolidated system report.