ECC Decoder Feedback Circuit for NAND Read Error Correction
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Solution Overview
Problem
Existing storage devices face challenges in effectively correcting error bits in data read from non-volatile memory devices, as current error correction codes struggle to enhance the reliability and efficiency of error correction operations.
Innovation Solution
An error correction circuit is introduced, comprising a first and second ECC decoder, a logic circuit, and a message regenerator, which perform multiple decoding operations and modify log likelihood ratios based on bit flip information to improve error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple ECC decoders exchange information to enhance error correction effectiveness, then the ability to correct error bits is improved, but the device complexity increases
Solution Approach 1:
The error correction system is segmented into multiple specialized ECC decoders (first ECC decoder for codeword-level correction, second ECC decoder for message data-level correction) that each handle specific aspects of error correction. This segmentation allows each decoder to be optimized for its specific function while collectively providing enhanced error correction capability without requiring a single overly complex decoder structure.
Solution Approach 2:
The patent implements a nested decoding structure where the second ECC decoder processes message data that is nested within the codeword processed by the first ECC decoder. The output from the second decoder is fed back to the first decoder for further processing, creating a nested information exchange pattern that enhances correction effectiveness while maintaining modular architecture.
2Measurement precision
If bit flip information is used to modify target LLR values, then the precision of error correction is improved, but the computational complexity increases
Solution Approach 1:
The system implements feedback mechanisms where bit flip information generated during the decoding process is fed back to modify the target log-likelihood ratio (LLR) values. The first logic circuit generates bit flip information by comparing intermediate results, and this feedback is used by the second logic circuit to adjust LLR values, creating a refined iterative correction process that improves precision through controlled feedback loops.
Solution Approach 2:
The patent dynamically changes the LLR parameters during the decoding process based on bit flip information. When bit flips are detected, the system modifies the magnitude and sign of target LLR values to reflect the corrected bit states. This parameter adjustment strategy allows the system to adaptively refine its error correction decisions without requiring a complete redesign of the decoding algorithm.
Data Source
AI summary
An error correction circuit includes a first ECC decoder configured to perform a first decoding operation on a codeword including first message data and second message data to generate a plurality of first sign data; a second ECC decoder configured to perform a second decoding operation on the first message data to generate a plurality of second sign data corresponding to the first message data; a first logic circuit bit configured to generate bit flip information indicating a number of times that the first message data and the plurality of second sign data are determined to be different values for each bit; and a second logic circuit configured to modify target sign data and a target reliability data based on the bit flip information, and provide the modified target sign data and the modified target reliability data to the first ECC decoder.