ECC Implementation in Fixed Bandwidth Memory Devices
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Solution Overview
Problem
Low power memory devices, commonly used in high temperature environments and IoT applications, face challenges in implementing Error Checking and Correction (ECC) due to their fixed x16 interface width, which requires significant redesigns and additional resources, making traditional ECC methods inefficient and costly.
Innovation Solution
The implementation of byte mode operation in low power memory devices allows for the use of ECC within a fixed channel width by selectively applying CAS signals to memory dies, enabling the combination of ECC bits with data bits without increasing the I/O interface width, thereby allowing ECC to be applied without additional memory devices or interface changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC is implemented in low power memory devices, then error detection and correction capability is improved, but device complexity and resource overhead increase significantly due to requiring additional memory devices or interface redesigns
Solution Approach 1:
The patent makes the existing x16 interface perform multiple functions by operating in byte mode, where the interface can dynamically allocate bits for both data transmission and ECC operations. The same physical interface serves dual purposes: transmitting 16 data bits in normal mode or 8 data bits plus 7 ECC bits in ECC mode, eliminating the need for dedicated ECC interface circuits.
Solution Approach 2:
The patent changes the operational parameters of the memory interface by introducing byte mode operation. This allows the interface width to be dynamically adjusted between x16 and x9 configurations through control signals, enabling ECC functionality without permanent hardware modifications. The interface can switch between different bit allocations based on operational requirements.
2Reliability
If ECC is implemented by adding a second memory device, then error correction capability is improved, but memory resource efficiency deteriorates due to nearly doubling system memory
Solution Approach 1:
The patent merges the ECC functionality with the existing memory device by utilizing byte mode operation. Instead of separating ECC functions into additional devices, the solution combines data storage and error correction capabilities within the same memory device, using the existing x16 interface to carry both data and ECC information simultaneously through dynamic bit allocation.
Solution Approach 2:
The same memory device and interface serve dual purposes: storing user data and providing error correction. The x16 interface dynamically allocates bits between data and ECC functions, making the memory device universally capable of both primary storage and error protection without requiring separate dedicated ECC hardware.
3Quantity of substance
If byte mode operation is used to enable ECC, then resource overhead is reduced, but manufacturing precision requirements increase due to selective CAS signal application
Solution Approach 1:
The patent introduces dynamic control to the memory interface through byte mode operation. Control signals dynamically adjust the operational mode of the interface, switching between x16 and x9 configurations based on whether ECC is needed. This dynamic adaptability allows the system to optimize resource usage while maintaining compatibility with existing hardware through software-controlled configuration.
Data Source
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AI summary
A multi-die memory device having fixed bandwidth interfaces can selectively connect portions of the interfaces of the multiple memory dies as a memory channel for the multi-die device. The selective application of the interface bits of the memory dies enables the application of ECC (error checking and correction) in memory devices that otherwise have insufficient connectors to exchange ECC information. The device includes circuitry to selectively apply CAS (column address select) signals to the memory dies to selectively connect the connectors of the memory dies. CAS selection can provide various configurations in which selected bits of a first memory die interface are combined with selected bit or bits of a second memory die interface to provide the device interface. The memory dies can operate in byte mode to apply only half of their data I/O (input/output) interface, with CAS doubled up to provide access to the memory arrays.