Semiconductor ECC Circuit Fuse-Based Address Replacement
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Solution Overview
Problem
Conventional semiconductor memory devices have limited error detection and correction capabilities due to the restricted number of parity bits, which restricts the number of DQ bits that can be verified and corrected.
Innovation Solution
A semiconductor device with a memory region and an error check and correction (ECC) region that includes a redundancy region with fuses, allowing for the detection of errors and replacement of defective addresses with redundancy lines, independent of the number of DQ bits, thereby enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC circuit with limited parity bits is used, then device complexity is reduced, but error detection and correction capability is limited
Solution Approach 1:
The patent transitions from traditional parity bit-based ECC to a fuse-based address replacement mechanism. Instead of adding more parity bits (horizontal expansion), the invention introduces a new dimensional approach by using fuses to store and replace defective addresses, fundamentally changing the ECC architecture from bit-level correction to address-level replacement.
Solution Approach 2:
The patent introduces fuses as an intermediary element between the memory array and the ECC logic. The fuses serve as a mediator that stores defective address information and enables replacement with redundancy line addresses, acting as a bridge that decouples the error correction function from the traditional parity bit approach.
2Reliability
If number of parity bits is increased to improve error correction capability, then error detection capability is improved, but the number of DQ bits that can be verified is restricted
Solution Approach 1:
The patent segments the error correction function into two independent parts: (1) parity bits for detecting data errors in DQ bits, and (2) fuses for replacing defective address bits. This segmentation allows each component to operate independently, enabling the system to correct both data errors and address errors without the traditional trade-off between correction capability and verifiable DQ bit capacity.
Solution Approach 2:
The fuse-based address replacement mechanism serves multiple functions: it stores defective address information, enables redundancy line selection, and provides address error correction. This multi-functional approach replaces what would traditionally require multiple layers of parity bits, thereby increasing the number of verifiable DQ bits while maintaining or improving overall error correction capability.
3Reliability
If fuse-based address replacement is implemented, then ECC capability is improved beyond 1-2 bit limitation, but device complexity increases
Solution Approach 1:
The patent creates a copy of the address space in the form of redundancy lines that mirror the structure of the main memory array. These redundancy lines are activated through fuse-based address replacement, allowing defective addresses to be copied to functional redundancy locations. This copying mechanism enables correction of multiple bit errors without proportionally increasing the complexity of the correction logic.
Data Source
AI summary
A semiconductor device includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.