Memory Row Hammer Refresh Using ECC-Guided Error Tracking
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Solution Overview
Problem
Semiconductor memory devices, particularly DRAMs, face issues with data loss due to leakage currents and adjacent cell degradation from frequent access, leading to increased power consumption and chip size overheads in existing row hammer attack defense mechanisms.
Innovation Solution
A semiconductor memory device that stores hammer addresses based on the degradation of memory cells, using a row hammer management circuit to count access frequencies and prioritize refresh operations for vulnerable cells, reducing power consumption and overheads by targeting intensive access rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed frequently to prevent data loss from leakage current, then data integrity is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on row-specific characteristics. Instead of uniform refresh across all rows, the system identifies rows with high access frequency (vulnerable to row hammer attacks) and applies enhanced refresh strategies specifically to those rows. This is achieved through monitoring access patterns and dynamically adjusting refresh parameters for affected rows only, thereby reducing overall power consumption while maintaining data integrity where most needed.
Solution Approach 2:
The patent implements dynamics by making refresh operations adaptive rather than static. The system continuously monitors access frequency of memory rows and dynamically adjusts refresh parameters in real-time. When a row is identified as being frequently accessed (indicating potential row hammer vulnerability), the refresh strategy for that specific row is dynamically modified to include additional protection mechanisms, while other rows continue with standard refresh patterns.
2Reliability
If row hammer attack defense mechanisms are implemented to protect against intensive access, then reliability is improved, but chip size overhead increases
Solution Approach 1:
The patent applies universality by designing a multi-functional monitoring and management circuit that serves multiple purposes: it tracks access frequency for row hammer detection, identifies vulnerable rows, and controls refresh operations. Rather than implementing separate dedicated circuits for each function, the system uses a unified approach where the same circuitry performs access monitoring, vulnerability assessment, and refresh coordination, thereby reducing the overall chip area required for attack defense mechanisms.
Solution Approach 2:
The system implements self-service by enabling the memory device to autonomously monitor its own access patterns and manage its own refresh operations without external intervention. The built-in monitoring circuit automatically detects high-access rows, identifies them as vulnerable to row hammer attacks, and applies appropriate refresh strategies independently, eliminating the need for additional external protection circuits and reducing chip overhead.
3Reliability
If access frequency monitoring is performed to identify vulnerable rows, then row hammer defense capability is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by combining multiple functions into a single integrated monitoring and management circuit. The circuit merges access frequency counting, vulnerability identification, and refresh control operations into one unified structure. By merging these functions rather than implementing them as separate modules, the system reduces the overall complexity of the defense mechanism while maintaining the capability to monitor access patterns and protect against row hammer attacks.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an error check and scrub (ECS) circuit, a row hammer management circuit and a refresh control circuit. The ECC engine generates an error generation signal based on a result of an ECC decoding. The ECS circuit generates scrubbing addresses and outputs at least one of the scrubbing addresses as an error address based on the error generation signal. The row hammer management circuit stores an error flag with a first logic level in count cells, compares counted values with different reference number of times based on a logic level of the error flag and outputs a hammer address. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address.