Multi-Level ECC Hash Grouping for Memory Error Correction
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Solution Overview
Problem
Existing error detection and correction methods in memory systems are inadequate for effectively handling transient and stochastic errors, particularly as memory size increases and error probabilities rise.
Innovation Solution
The implementation of a multi-level error correction coding scheme where each memory bit is associated with multiple error correction codes (ECCs), grouped as ECC groups, to enhance error detection and correction capacity without increasing complexity or parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single-ECC error correction methods are used, then the memory system maintains simplicity and compatibility, but the transient and stochastic fault correction capacity is insufficient as memory size increases
Solution Approach 1:
The patent divides the memory system into multiple ECC groups, where each ECC group contains multiple ECCs (Error Correction Codes) organized in hash groups. This segmentation allows the system to handle different types of errors (transient and stochastic) with specialized ECCs while maintaining overall system manageability. Each ECC group operates semi-independently, improving fault correction capacity without overwhelming system complexity.
Solution Approach 2:
The patent creates a multi-functional ECC structure where each ECC group serves multiple purposes: correcting transient errors, correcting stochastic errors, and providing redundancy. The multiple hash groupings within each ECC group enable the same structural framework to handle various error types universally, enhancing reliability without requiring entirely separate correction mechanisms for each error type.
2Reliability
If multiple ECCs are associated with each memory bit, then error detection and correction capacity is enhanced, but the system complexity and number of parity bits increases
Solution Approach 1:
The patent organizes multiple ECCs into hierarchical hash groups rather than simply increasing the number of ECCs linearly. This creates a multi-dimensional structure where ECCs are grouped by hash functions, allowing the system to access and apply appropriate ECCs based on error patterns. This dimensional organization enhances correction capacity while maintaining systematic control over complexity.
Solution Approach 2:
The patent changes the organizational parameters of ECCs by introducing hash groupings with specific parameters (hash functions, group sizes, and selection criteria). Instead of uniformly applying multiple ECCs to all memory bits, the system dynamically selects and applies ECCs based on hash group parameters, optimizing the balance between correction capacity and resource utilization.
3Ease of manufacture
If existing memory designs and error detection algorithms are maintained for compatibility, then ease of implementation is preserved, but the capacity to handle increasing error probabilities in larger memory systems is limited
Solution Approach 1:
The patent implements preliminary error correction by organizing ECCs into hash groups that can be pre-selected and applied based on error patterns before full correction is attempted. This preliminary action using structured hash groupings allows the system to quickly address common error types while maintaining compatibility with existing correction algorithms for more complex cases.
Solution Approach 2:
The patent introduces hash groupings as an intermediary layer between traditional ECCs and the memory system. This intermediary structure maintains compatibility with existing memory designs by preserving the basic ECC interface, while simultaneously enabling enhanced error correction capabilities through the organized multiple-ECC approach. The hash group structure acts as a mediator that bridges legacy compatibility and advanced correction needs.
Data Source
AI summary
Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.