Error Correction Using Historical Bit Error Data
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Solution Overview
Problem
Current error correction systems in data storage devices rely on initial bit line defect information generated during fabrication, which may not identify 'weak' bit lines that become defective during the operational lifetime, leading to potential data errors.
Innovation Solution
The system generates reliability information based on historical bit error data, tracking bit errors over the device's lifetime to identify both defective and weak bit lines, enabling faster and more power-efficient decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If initial bit line defect information from fabrication is used for error correction, then defective bit lines detected during manufacturing can be corrected, but weak bit lines that become defective during operational lifetime cannot be identified
Solution Approach 1:
The system performs preliminary error tracking and reliability assessment during the operational lifetime of the memory device. By continuously monitoring bit error rates and maintaining historical error data, the system proactively identifies weak bit lines before they cause critical failures, enabling adaptive error correction that evolves with device aging.
Solution Approach 2:
The system implements a feedback mechanism where decoded data and bit error information are continuously fed back to update reliability metrics for each bit line. This feedback loop allows the system to adaptively adjust error correction strategies based on actual performance data, identifying both initially defective and subsequently weakened bit lines throughout the device lifetime.
2Productivity
If traditional decoding without reliability information is performed, then all data can be decoded uniformly, but decoding speed and power consumption are suboptimal
Solution Approach 1:
The system applies local quality by differentiating decoding processes based on bit line reliability. High-reliability bit lines undergo streamlined decoding with fewer computational steps, while low-reliability bit lines receive enhanced error correction processing. This localized approach optimizes overall decoding performance and power efficiency by avoiding uniform over-processing of all data.
Solution Approach 2:
The system employs partial action by selectively applying full error correction only to data from low-reliability bit lines, while using reduced correction for high-reliability bit lines. This partial application of correction measures reduces computational overhead and power consumption while maintaining adequate error protection where most needed.
3Measurement precision
If multiple read voltages are applied to generate soft bits for error correction, then accurate probability information is obtained, but read operation time and power consumption increase
Solution Approach 1:
The system performs preliminary reliability assessment using historical error data and bit line defect information before executing multiple read voltage operations. By pre-identifying high-reliability bit lines, the system can skip or reduce the number of read voltage applications for those bit lines, while applying full multi-voltage reading only to low-reliability bit lines that require enhanced verification.
Data Source
AI summary
A data storage device includes a memory including a plurality of storage elements. The data storage device further includes a controller coupled to the memory. The controller includes an error correction code (ECC) engine. The controller further includes a reliability engine configured to access historical bit error data. The historical bit error data includes a first count of bit errors associated with a first set of storage elements of the plurality of storage elements. The reliability engine is configured to generate reliability information based on the historical bit error data and to provide the reliability information to the ECC engine.