ECC Interleaving for Resistive Memory Bit Error Rate Equalization
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Solution Overview
Problem
Non-volatile resistive memory devices face challenges in maintaining data integrity due to bit error rate (BER) variations across memory cells, which burden the error correction circuit, as the number of detectable bit errors exceeds the correction capacity, leading to inefficient data rewriting and potential data loss.
Innovation Solution
The implementation of an error correction code (ECC) interleaving operation that divides ECC sectors into sub-sectors and writes them to memory areas with varying bit error rates, specifically a high BER area and a low BER area, to equalize the bit error rate and reduce the burden on the error correction circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in memory cells with varying resistance values, then storage capacity is increased, but bit error rate varies across different memory locations creating unequal error distribution
Solution Approach 1:
The memory array is divided into multiple memory blocks, each with different target resistance values. This segmentation allows the system to store data across multiple locations while managing bit error rates differently in each block, thereby achieving both high storage capacity and controlled error distribution.
Solution Approach 2:
Different memory blocks are assigned different target resistance values based on their specific characteristics and error rates. This local quality approach allows each block to be optimized for its particular performance characteristics, enabling the system to accommodate varying reliability across different storage locations while maintaining overall storage capacity.
2Reliability
If error correction code capacity is increased to handle higher bit error rates, then data reliability is improved, but device complexity increases
Solution Approach 1:
The system performs preliminary actions by selecting and optimizing target resistance values for different memory blocks before data storage occurs. This preliminary optimization of resistance distribution reduces the actual bit error rates that occur during operation, thereby reducing the burden on the error correction circuit and avoiding the need for overly complex ECC capabilities.
Solution Approach 2:
The system changes the resistance parameter distribution across different memory blocks to optimize bit error rates. By adjusting target resistance values as a key parameter, the system achieves better error characteristics without requiring increased error correction code capacity, thus maintaining device simplicity while improving data reliability.
3Reliability
If frequent data rewriting is performed to correct bit errors, then data integrity is maintained, but storage efficiency decreases due to time loss
Solution Approach 1:
The system performs preliminary optimization of resistance distribution and target resistance value selection before data is written to memory. This preliminary action reduces the likelihood of bit errors occurring in the first place, thereby reducing the frequency of required rewrites and maintaining both data integrity and storage efficiency.
Solution Approach 2:
Instead of repeatedly rewriting the same data to correct errors, the system uses error correction codes that create a copy of the data with embedded correction information. This allows the original data to remain in memory without frequent rewrites, while the ECC copy provides the necessary error correction capability, thereby maintaining data integrity without sacrificing storage efficiency.
Data Source
AI summary
Provided is a bit error rate equalizing method of a memory device. The memory device selectively performs an error correction code (ECC) interleaving operation according to resistance distribution characteristics of memory cells, when writing a codeword including information data and a parity bit of the information data to a memory cell array. In the ECC interleaving operation according to one example, an ECC sector including information data is divided into a first ECC sub-sector and a second ECC sub-sector, the first ECC sub-sector is written to memory cells of a first memory area having a high bit error rate (BER), and the second ECC sub-sector is written to memory cells of a second memory area having a low BER.