ECC Circuit Latch Decoupling for Memory Read Timing Margin
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in managing timing margins and layout area while sharing logic trees for both write and read operations in error correction circuits, leading to difficulties in ensuring high fidelity of data readout.
Innovation Solution
The implementation of a shared logic tree for error correction circuits that decouples the read and write paths, allowing the read parity bit to be held in a latch independently of write operations, thereby increasing timing margins and optimizing circuit efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a shared logic tree is used for both write and read operations in error correction circuits, then layout area is reduced, but timing margin deteriorates due to coupling between read and write paths
Solution Approach 1:
The patent divides the error correction circuit into separate read path and write path components, even though they share the logic tree. The read path includes a read parity bit latch and XOR gates that are distinct from write path components. This segmentation allows independent timing optimization for read operations while maintaining area efficiency through sharing the logic tree structure.
2Device complexity
If read and write paths are coupled in error correction circuits, then device complexity is reduced, but reliability deteriorates due to interference between operations
Solution Approach 1:
The patent introduces a read parity bit latch as an intermediary component between the shared logic tree and the read path. This latch holds the read parity bit independently, preventing direct coupling effects from write operations. The XOR gates then compare this held parity bit with new parity bits, ensuring reliable error detection while maintaining circuit efficiency through the shared logic tree.
3Reliability
If timing margin is increased by decoupling read and write paths, then reliability is improved, but layout area increases due to additional latches and path separation
Solution Approach 1:
The shared logic tree serves multiple functions: it generates parity bits for write operations and generates new parity bits for read operations. By making the logic tree universal and shared between read and write paths, the patent reduces the need for separate dedicated logic trees, thereby minimizing area overhead while still achieving path decoupling through the intermediary latch structure.
Data Source
AI summary
Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.