ECC Locator Merging for High-RAS Memory Without Lockstepping
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Solution Overview
Problem
Conventional memory systems face inefficiencies and high costs in achieving high reliability, availability, and serviceability (RAS) due to resource-intensive features like lockstepping and capacity penalties, particularly in high-end computer servers.
Innovation Solution
A mechanism for merging error-correction code (ECC) techniques, such as x4 Double Device Data Correction (DDDC) and x8 Single Device Data Correction (SDDC), is implemented without lockstepping, allowing for efficient failure handling and correction across memory channels and ranks, using ECC merging logic to manage device failures and maintain bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rank sparing is used to cover for failed memory devices, then reliability is improved, but capacity efficiency deteriorates due to holding entire ranks in reserve
Solution Approach 1:
The patent merges ECC locators from multiple memory channels into a single consolidated ECC structure. By combining the error correction capabilities of multiple channels' ECC locators, the system can correct errors across broader memory regions without requiring separate reserve ranks for each channel, thus improving capacity efficiency while maintaining reliability
Solution Approach 2:
The consolidated ECC structure serves multiple functions simultaneously: it protects data from multiple memory channels, provides unified error correction capability, and eliminates the need for channel-specific reserve ranks. This multi-functional approach allows the same ECC resources to serve broader protection needs without proportionally increasing capacity costs
2Reliability
If lockstepping is used for double device data correction, then reliability is improved, but power consumption increases and bandwidth is reduced
Solution Approach 1:
The patent merges ECC locators from multiple memory channels into a single consolidated structure that can handle double device errors without requiring lockstepping operations. By consolidating the error correction logic and data paths, the system achieves DDDC capability with single-channel access patterns, eliminating the synchronized dual-channel operations that cause high power consumption and bandwidth reduction
Solution Approach 2:
The patent extracts the essential error correction functionality from the lockstepping mechanism. By separating the ECC locator merging and correction logic from the lockstepping data synchronization requirements, the system achieves reliable double device correction without inheriting the power and bandwidth penalties of full lockstepping operations
3Reliability
If lockstepping is used for double device data correction, then reliability is improved, but processing bandwidth is reduced
Solution Approach 1:
The patent merges ECC locators from multiple memory channels into a single consolidated ECC structure. This merging allows the system to process error correction for double device errors using a unified data path that maintains full bandwidth utilization, rather than splitting operations across locked-step channels that would halve the effective bandwidth
Solution Approach 2:
The patent segments the error correction process into independent stages: ECC locator extraction from individual channels, merging of locators in logic circuitry, and correction application. This segmentation allows parallel processing of error detection and correction without requiring synchronized lockstepping, thereby preserving bandwidth while achieving reliable DDDC
Data Source
AI summary
A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.