Compute-Class ECC Logic for In-Memory Error Correction
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Solution Overview
Problem
Current error correction methods for in-memory computations are inefficient as they require data to be sent to a memory controller for error correction, consuming energy and time, and can be ineffective when the number of error bits is high, especially in architectures where computations are performed within the memory.
Innovation Solution
Implementing a compute-class ECC logic unit within the media access circuitry on the same die as the memory media to perform error correction locally, using algorithms like BCH codes, and adjusting reference voltages to manage error bits, allowing for efficient in-memory compute operations and reducing the need for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is sent to memory controller for error correction, then error correction capability is provided, but energy consumption increases and time is lost
Solution Approach 1:
The patent segments the error correction function from the centralized memory controller and distributes it to individual compute units within the memory array. Each compute unit contains its own ECC logic to perform local error correction on data it reads, eliminating the need to transfer data to the memory controller for correction. This segmentation resolves the contradiction by enabling error correction capability while avoiding the energy and time costs of data transfer.
Solution Approach 2:
The patent introduces a new spatial dimension for error correction operations by implementing compute units directly within the memory array structure. Instead of the traditional single-point correction at the memory controller, error correction capability is distributed across multiple dimensions within the memory fabric itself. This allows local correction without data movement, resolving the energy-time tradeoff.
2Reliability
If data is sent to memory controller for error correction, then error correction is performed, but computation efficiency is diminished
Solution Approach 1:
The patent segments the memory system into autonomous compute units, each capable of independent error correction. This allows computation and error correction to occur simultaneously at the data location without requiring centralized processing, thereby maintaining computation efficiency while ensuring reliability.
Solution Approach 2:
Each compute unit is equipped with its own ECC logic to perform self-service error correction on data it reads from the memory array. This eliminates the need to send data to the memory controller for correction, allowing compute units to maintain their computational workflow without interruption or efficiency loss.
3Device complexity
If compute units perform operations on raw data without local error correction, then device complexity is reduced, but data reliability decreases
Solution Approach 1:
The patent adds error correction capability to each compute unit without creating a completely new complex system. The ECC logic is integrated into the existing compute unit architecture, allowing data reliability to be improved while maintaining relatively simple device complexity through modular design.
4Reliability
If larger data sets are used for ECC protection, then error correction strength is improved, but overhead increases
Solution Approach 1:
The patent segments the data processing into smaller units at the compute unit level, allowing ECC to be applied to appropriately sized data sets. This segmentation enables effective error correction strength while managing overhead, as each compute unit handles its own data with embedded ECC rather than requiring large centralized data sets.
Data Source
AI summary
Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.