ECC Block Matrix Layout for Diagonal Parity Error Correction
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Solution Overview
Problem
Existing semiconductor devices face challenges in effectively correcting error patterns due to the influence of concatenated BCH codes, which can lead to an error floor and difficulty in identifying specific error bits, and frequent read operations can deteriorate memory cells and shorten their lifetime.
Innovation Solution
A semiconductor device with an error correction code (ECC) unit that generates data block groups and parity blocks, arranges them in a matrix, and adds parity information to encode data, allowing for efficient error detection and correction using a processor and ECC encoder, decoder, and memory interface unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If concatenated BCH code is used for error correction, then error detection and correction capability is improved, but error floor increases and specific error bit identification becomes difficult
Solution Approach 1:
The patent divides the data block into multiple sub-blocks and generates separate parity blocks for each sub-block. This segmentation allows the system to identify which specific sub-block contains the error, thereby locating the erroneous bit position more precisely while maintaining the error correction capability provided by the parity blocks.
2Reliability
If multiple read and verify operations are performed on memory cells, then data reliability is improved, but memory cell lifetime is reduced
Solution Approach 1:
The patent performs error correction at the time of data writing by comparing the written data with the generated parity information and correcting any errors before the data is stored. This preliminary correction eliminates the need for subsequent read-verify-correct cycles, thereby reducing memory cell stress and extending lifetime while ensuring data reliability.
3Productivity
If data block matrix with diagonal arrangement of data block groups is generated, then error pattern correction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces a diagonal arrangement dimension by organizing data blocks and parity blocks along diagonal lines in the data block matrix. This diagonal structure enables more efficient error pattern detection and correction by creating unique parity relationships, while the systematic generation method keeps the implementation complexity manageable.
Data Source
AI summary
A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.