ECC Check Matrix Truncation for Lower-Logic Multi-Bit Correction
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Solution Overview
Problem
Existing error correction codes (ECC) for memory systems require extensive logic and resources to implement multi-bit error correction, which can be inefficient and complex, especially in emerging memory technologies like MRAM and ReRAM.
Innovation Solution
The use of a systematic check matrix to reduce logic requirements by transforming the generation matrix into a systematic form, truncating rows with higher weights, and forming a truncated parity matrix to minimize the number of logic gates in the error correction circuit, thereby optimizing the error correction process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are used for multi-bit error correction, then error correction capability is improved, but logic complexity and resource requirements increase
Solution Approach 1:
The patent segments the error correction process by separating syndrome calculation from error pattern identification. The systematic check matrix divides the code structure into information bits and check bits, allowing independent processing of syndrome generation and error correction logic, thereby reducing overall circuit complexity while maintaining multi-bit error correction capability
Solution Approach 2:
The patent transforms the generation matrix into systematic form by applying parameter changes to the matrix structure. This transformation modifies the arrangement of bits and check bits according to specific mathematical rules, enabling simplified syndrome calculation and reducing the logic gates required for error correction operations
2Reliability
If traditional error correction codes are used for multi-bit error correction, then error correction capability is improved, but resource consumption increases
Solution Approach 1:
The patent extracts and eliminates redundant logic operations by using the systematic check matrix structure. By organizing the code in systematic form, the patent removes unnecessary calculations and focuses only on the essential syndrome bits needed for error correction, thereby reducing resource consumption while maintaining correction capability
Solution Approach 2:
The patent applies partial action by calculating only the necessary syndrome bits required for multi-bit error correction rather than processing all possible bit combinations. This selective approach reduces the quantity of computational resources needed while achieving the required error correction strength
3Reliability
If extensive logic is used for error correction, then error correction capability is improved, but circuit structure complexity increases
Solution Approach 1:
The patent segments the circuit structure into distinct functional blocks: syndrome calculation units, error pattern detection logic, and correction execution units. This segmentation allows each block to be optimized independently and simplifies the overall circuit architecture by clearly defining interfaces and data flow between components
Solution Approach 2:
The patent performs preliminary organization of the code structure by transforming the generation matrix into systematic form before implementation. This preliminary action pre-arranges the bits and check bits in an optimal configuration that simplifies subsequent circuit design and reduces the complexity of the error correction logic
Data Source
AI summary
A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix (G matrix) formed of a concatenation of a parity matrix (P matrix) and an identity matrix; determining a number of rows in the P matrix for a truncated P matrix in view of a correcting strength and a number of data bits; selecting a first subset of rows and a second subset of rows in the P matrix, wherein a first sum of row weights of each row in the first subset of rows is equal to or less than a second sum of row weights of each row in the second subset of rows; and generating the truncated P matrix by keeping the first subset of rows of the P matrix so as to minimize a number of logic gate operations.