ECC Parity Matrix Switching for Flash Storage Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The refinement of flash memory fabrication technology and the adoption of multi-level cell (MLC) technology have reduced the fabrication cost of storage media but compromised their reliability and durability.
Innovation Solution
A data storage device with an error correction code (ECC) engine that stores a first parity check matrix for normal operation and switches to a second parity check matrix from firmware during specific operation modes to perform error correction, enhancing reliability and adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If flash memory fabrication technology is refined and MLC technology is adopted, then fabrication cost is reduced, but reliability and durability are degraded
Solution Approach 1:
The ECC engine dynamically switches between different parity check matrices based on operation mode. A first parity check matrix is used during normal operation, while a second parity check matrix is extracted from firmware and used during abnormal operation modes. This dynamic adaptation allows the system to maintain higher reliability when needed while keeping fabrication costs low through standard MLC technology.
Solution Approach 2:
The system changes the code rate parameter by selecting different parity check matrices. The first parity check matrix corresponds to a first code rate for normal operation, while the second parity check matrix corresponds to a second code rate for abnormal operation. This parameter change enables adaptive error correction capability without changing the physical storage medium.
2Device complexity
If a single parity check matrix is used for all operation modes, then device complexity is reduced, but adaptability to different operation modes is limited
Solution Approach 1:
The ECC engine is designed with multi-functionality to handle both normal and abnormal operation modes. It can operate with a first parity check matrix stored in the device for normal operations, and also extract and use a second parity check matrix from firmware for abnormal operations. This universal design allows one ECC engine to perform multiple error correction functions without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The firmware acts as an intermediary that contains the second parity check matrix. When abnormal operation is detected, the system retrieves the appropriate parity check matrix from the firmware rather than having it permanently stored in the ECC engine. This intermediary approach provides adaptability while keeping the ECC engine structure relatively simple.
Data Source
AI summary
A data storage device may include: a storage configured to store user data, firmware and a boot code; and a controller configured to control data exchange with the storage, and comprising an error correction code (ECC) engine configured to perform error correction during the data exchange, wherein the ECC engine stores a first parity check matrix, performs error correction on data exchanged with the storage based on the first parity check matrix during a first operation mode, and performs error correction on data exchanged with the storage based on a second parity check matrix extracted from the firmware during a second operation mode.