ECC Memory Layout with Single-Access Reads for Lower Overhead
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Solution Overview
Problem
The use of error correction codes in memory devices increases the memory surface area requirement, leading to higher leakage currents and costs, especially in low-consumption products, and existing systems double memory access consumption when error correction codes are used.
Innovation Solution
A memory system with separate regions for data and error correction code check bits, where check bits are read and stored in a register during a single memory access, reducing the need for additional memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code check bits are stored in a separate memory region, then data integrity is improved, but memory surface area increases by 22%
Solution Approach 1:
The patent implements dynamic reconfiguration of memory regions allowing the second memory region to serve dual purposes: storing error correction code check bits when ECC is enabled, and storing additional data when ECC is disabled. This dynamic adaptation eliminates the static 22% surface area penalty by making the memory allocation flexible based on operational requirements.
Solution Approach 2:
The second memory region is designed with multi-functionality, capable of storing either error correction code check bits or additional data depending on the application requirements. This universal design allows the same physical memory space to serve different functions, thereby reducing the overall memory surface area needed while maintaining data integrity when ECC is required.
2Reliability
If error correction code check bits are stored in a separate memory region, then error detection capability is improved, but leakage current increases due to unused memory surface area
Solution Approach 1:
The memory system dynamically configures the second memory region based on whether ECC functionality is required. When ECC is disabled, the region is repurposed for data storage, ensuring that no memory surface area remains unused and thereby minimizing leakage current while maintaining error detection capability when needed.
Solution Approach 2:
The patent changes the operational parameter of the second memory region from a fixed ECC-only storage to a configurable storage that can hold either check bits or data. This parameter change allows the system to optimize between error detection capability and energy consumption by activating ECC functionality only when required.
3Productivity
If check bits are read during the same memory access as data, then access efficiency is improved, but consumption doubles due to accessing both memory regions
Solution Approach 1:
The patent merges the reading operations of data and check bits into a single memory access cycle. By configuring the memory system to read from both the first memory region (data) and second memory region (check bits) simultaneously during the same access cycle, the system improves access efficiency without proportionally increasing consumption, as the overhead is amortized across a unified access operation.
Solution Approach 2:
The system performs preliminary configuration of the memory regions and access paths to enable simultaneous reading of data and check bits. By pre-establishing the dual-region access capability and configuring the memory controller accordingly, the system prepares the infrastructure in advance to handle combined reads efficiently, avoiding the need for separate sequential accesses that would double the consumption.
Data Source
AI summary
A method for managing the consumption of a memory device includes performing a first reading of data in a first portion of a first memory area of the memory device. During a same memory access, error correction code check bits are read from a second portion of a second memory area of the memory device. The error correction check bits include error correction check bits that are associated with the data in the first portion of the first memory area and other error correction code check bits associated with other data. All of the other error correction code check bits are stored in a register, and the other data in the first portion of the first memory area is read. The error correction code bits associated with the other data are extracted from the register.