Dynamic Writable Region Adjustment in ECC Memory Buffers
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Solution Overview
Problem
Existing memory devices struggle to dynamically adjust the writable region based on the operational state of the error-correcting code (ECC) circuit, leading to inefficiencies in data storage and retrieval processes.
Innovation Solution
A memory system that includes a semiconductor memory unit, a controller circuit, and an ECC circuit, where the ECC circuit generates error correction codes and the controller adjusts the maximum column address of the page accessible from the host based on whether the ECC circuit is enabled or disabled, allowing for flexible setting of writable areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the writable region is fixed to the maximum address space, then the host can access the entire address space, but the ECC parity cannot be securely stored when ECC is enabled
Solution Approach 1:
The patent implements a dynamic writable region management mechanism where the maximum column address of the data buffer is adjusted based on the ECC circuit's operational state. When ECC is enabled, the writable region is reduced to exclude the ECC parity area; when ECC is disabled, the full address space becomes accessible. This dynamic adjustment resolves the contradiction by making the system adaptable to different operational modes while maintaining clear address space management through controller-mediated access control.
2Reliability
If the writable region is reduced to accommodate ECC parity, then ECC parity can be securely stored, but the host access area is limited
Solution Approach 1:
The patent applies local quality differentiation by dividing the data buffer into distinct functional regions: a host-accessible data area and an ECC parity storage area. The ECC parity is stored in a specific region (e.g., higher address space) that is protected from direct host writes when ECC is enabled. This localized separation ensures reliable ECC parity storage while maintaining adequate host access area for actual data operations, resolving the contradiction between reliability and accessibility.
3Ease of operation
If the maximum column address is dynamically changed based on ECC state, then writable area can be appropriately set, but additional control logic is required
Solution Approach 1:
The controller automatically performs the task of adjusting the maximum column address based on the ECC circuit's enable state, without requiring explicit host commands or manual configuration. The controller monitors the ECC state and self-adjusts the writable region boundaries, thereby simplifying host operation (host只需发起写入命令，无需手动调整地址空间) while implementing the necessary control logic within the controller itself. This self-service mechanism resolves the contradiction by hiding complexity from the host while maintaining operational simplicity.
Data Source
AI summary
A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.