ECC Memory System Byte Write via Interleaved Data Multiplexing
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Solution Overview
Problem
Conventional error correction code (ECC) memory systems require additional memory devices and are inefficient in byte write operations, leading to increased costs and board area, as well as potential memory integrity issues due to the need for read/modify/write operations.
Innovation Solution
A memory controller scheme that virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory, enabling efficient byte write operations and reducing the footprint of ECC memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC memory systems are used, then memory error detection and correction is provided, but additional memory devices are required increasing component costs and board area
Solution Approach 1:
The patent combines data and ECC information into a single integrated memory structure. Instead of using separate memory devices for data and ECC, the system interleaves ECC bits with data bits within the same memory array, allowing both to be stored and accessed together in a unified structure that reduces overall memory footprint and board area.
Solution Approach 2:
The memory system is designed to serve multiple functions within a single structure. The same memory array stores both user data and ECC information, and the same memory interface handles both data and ECC operations. This multi-functional approach eliminates the need for dedicated separate memory devices for ECC operations.
2Reliability
If conventional ECC memory systems are used, then memory error detection and correction is provided, but component costs increase due to additional memory devices
Solution Approach 1:
The patent combines data and ECC information into a single integrated memory structure. Instead of using separate memory devices for data and ECC, the system interleaves ECC bits with data bits within the same memory array, allowing both to be stored and accessed together in a unified structure that reduces overall memory footprint and board area.
Solution Approach 2:
The memory system is designed to serve multiple functions within a single structure. The same memory array stores both user data and ECC information, and the same memory interface handles both data and ECC operations. This multi-functional approach eliminates the need for dedicated separate memory devices for ECC operations.
3Reliability
If conventional ECC memory systems are used, then error correction is provided, but byte write operations are inefficient requiring read/modify/write cycles
Solution Approach 1:
The patent segments the ECC calculation and update process to operate at the byte level rather than requiring full read/modify/write cycles. By organizing memory into banks and using segmented address lines, the system can independently update individual bytes with their corresponding ECC bits without affecting other data, enabling efficient byte-granularity write operations.
Solution Approach 2:
The system performs preliminary ECC calculation and preparation before the write operation is completed. ECC bits are calculated in advance for each byte, and the memory structure is pre-configured to allow direct byte updates without requiring subsequent read/modify/write cycles, thus improving write efficiency.
Data Source
AI summary
A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.