ECC Memory Error Correction via Cache Tracking

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Solution Overview

Problem

High-capacity memories face data retention challenges due to increased error rates from manufacturing defects, soft errors, and wear and tear, affecting yield and reliability, which existing error correction techniques struggle to address effectively.

Innovation Solution

A system employing Error Correction Code (ECC) with a cache memory to detect and correct errors, enabling ECC expansion to correct multi-bit errors, and marking data as uncorrectable when error limits are exceeded, with a refresh operation and ECC scheme adaptation to maintain memory reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory geometries are made smaller to increase capacity and density, then memory capacity and density are improved, but data retention and reliability deteriorate due to increased error rates

Engineering Contradiction:
Improvememory capacityVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory system is segmented into multiple components: error detection logic, error correction logic (ECC), cache memory for storing error information, and refresh operations. This segmentation allows each component to specialize in handling specific aspects of error management, thereby maintaining reliability in high-capacity memories.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary error detection and catalogs error locations before errors become critical. By proactively identifying and recording error positions in the cache, the system can apply corrective refresh operations or ECC corrections in advance, preventing data loss and maintaining reliability in high-density memory structures.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional error correction techniques are used, then some errors are corrected, but multi-bit errors and wear-induced errors cannot be effectively addressed

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror handling coverage
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The error correction system is made dynamic and adaptive. The cache memory stores real-time error location information that is updated continuously. Based on the cataloged error patterns, the system dynamically determines whether to apply refresh operations, ECC correction, or mark data as uncorrectable. This dynamic adaptation enables effective handling of various error types including multi-bit errors and wear-induced errors that static traditional ECC cannot address.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements feedback mechanisms where error detection results are stored in the cache and used to guide subsequent correction actions. The error information feedback loop allows the system to learn from detected errors and adjust its correction strategy, enabling it to handle increasingly complex error patterns including multi-bit and wear-induced errors that exceed traditional ECC capabilities.

Inventive Principle:
Principle #23Feedback

3Reliability

If error correction code (ECC) is enabled for all data, then error detection and correction are improved, but memory overhead and complexity increase

Engineering Contradiction:
Improveerror detection and correctionVSAvoidmemory overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of uniformly applying ECC to all memory data, the system applies error correction selectively based on local error conditions. The cache memory stores error information for specific memory locations, and correction actions are targeted only to affected regions. This local quality approach reduces overall system complexity and overhead while maintaining high reliability where errors are actually present.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The cache memory serves multiple functions: it stores error location information, tracks error patterns, guides refresh operations, and supports ECC correction decisions. This multi-functionality reduces the need for separate dedicated structures for each error handling task, thereby reducing overall memory overhead and complexity while maintaining comprehensive error detection and correction capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9772901B2Memory reliability using error-correcting code
Publication Date: 2017.09.26 NXP USA INC
  • US9772901B2 patent drawing
  • US9772901B2 patent drawing
  • US9772901B2 patent drawing

AI summary

A method and system are provided for error correction in a memory. Error correction code (ECC) for data stored in a portion of the memory is enabled. A location and number of errors for the portion of the memory is then stored. It is determined if the number of errors exceeds a predetermined number of errors. If the number of errors exceeds the predetermined number, then the data stored in the portion of the memory is refreshed. If refreshing does not correct the errors, then a different ECC may be used.