ECC Memory Testing with Error Address Recording
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current testing methods for ECC memory are unable to detect multi-bit errors and determine error numbers, leading to uncontrolled error tolerance.
Innovation Solution
A memory apparatus with a testing module that includes a test pattern generator, first and second judgment circuits, and an error recording unit, which generates test patterns, reads data bits, determines errors, records error addresses, and compares them to determine multi-bit errors, and optionally uses a counter to control error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a common testing algorithm is adopted for ECC memory, then the testing process is simple, but multi-bit errors cannot be detected
Solution Approach 1:
The testing module is divided into multiple specialized units: a test pattern generator for creating test data, a first judgment circuit for detecting single-bit errors, an error recording unit for storing error addresses, and a second judgment circuit for detecting multi-bit errors by comparing addresses. This segmentation allows each unit to perform its specific function efficiently, enabling comprehensive error detection while maintaining testability.
Solution Approach 2:
The error recording unit acts as an intermediary between the first judgment circuit and the second judgment circuit. It stores error addresses detected by the first judgment circuit and makes them available for comparison by the second judgment circuit, enabling the detection of multi-bit errors without complicating the overall testing process.
2Ease of manufacture
If current testing methods are used for ECC memory, then the testing implementation is straightforward, but error number and error status cannot be determined
Solution Approach 1:
The testing module implements feedback mechanisms where the first judgment circuit provides error address information to the error recording unit, and the second judgment circuit compares recorded addresses with new errors to determine multi-bit error status. This feedback loop enables comprehensive error tracking and status determination while maintaining a structured, implementable testing process.
Solution Approach 2:
The patent replaces complex mechanical or manual error tracking methods with electronic circuit implementations. The judgment circuits and error recording unit use electronic signal processing and digital logic to automatically detect, record, and analyze errors, providing complete error status information without manual intervention while keeping the implementation straightforward.
3Reliability
If ECC logic circuit is enabled for testing, then error correction is performed, but error tolerance cannot be controlled
Solution Approach 1:
The testing module performs preliminary error detection and recording before error correction is applied. By detecting and recording errors in advance, the system can determine error status and multi-bit error conditions, enabling controlled error tolerance assessment before the ECC logic circuit corrects the errors.
Solution Approach 2:
The testing module performs partial testing by focusing on specific error detection functions rather than complete error correction. The first judgment circuit detects single-bit errors, the error recording unit stores error addresses, and the second judgment circuit detects multi-bit errors, providing sufficient error information for tolerance control without requiring full ECC correction functionality during testing.
Data Source
AI summary
A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.