ECC Memory Error Determination for 1-Bit and 2-Bit Correction
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Solution Overview
Problem
As memory capacity increases, it becomes increasingly difficult to produce memory chips with no defective memory cells, necessitating the use of redundancy memory cells and error correction codes (ECC) to correct errors in memory cells.
Innovation Solution
A memory system incorporating an ECC engine that generates and applies error correction codes during encoding and decoding operations, and an error determination circuit that identifies 1-bit and 2-bit errors based on specific patterns in syndrome values generated by the ECC engine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but the probability of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by generating error correction codes during the write operation before data is stored in memory. The ECC engine encodes the write data and stores both the encoded data and syndrome values in the memory core, so that when data is read, the pre-stored syndrome values can be immediately used for error detection and correction without requiring additional computation time.
2Reliability
If error correction code engine is used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the syndrome values into multiple portions (first syndrome portion, second syndrome portion, third syndrome portion, etc.) corresponding to different bit positions of the encoded data. Each syndrome portion is stored in association with specific data bits, allowing the error determination circuit to efficiently identify error locations by examining only the relevant syndrome portions rather than processing all syndrome bits uniformly.
Solution Approach 2:
The patent organizes syndrome values in a multi-dimensional structure where syndrome portions are arranged according to their correspondence with data bit positions. The error determination circuit uses this dimensional organization to quickly identify which data bits may contain errors by comparing syndrome patterns against predetermined patterns, reducing the computational complexity of error detection.
3Measurement precision
If comprehensive error detection is implemented, then measurement precision is improved, but operation complexity increases
Solution Approach 1:
The patent implements partial action by having the error determination circuit focus on detecting only specific error types (1-bit errors and 2-bit errors) rather than attempting to detect and correct all possible error patterns. The circuit uses predetermined patterns to efficiently identify these common error types, providing sufficient error detection capability for practical applications while keeping the determination process manageable.
Data Source
AI summary
A memory includes a memory core, an error correction code (ECC) engine, and an error determination circuit. The ECC engine is configured to generate an error correction code to be stored in the memory core together with write data by using the write data during an encoding operation, and to correct an error of read data read from the memory core using the error correction code read from the memory core during a decoding operation. The error determination circuit is configured to determine that, during the decoding operation, a 1-bit error exists when upper index portions of syndromes generated by the ECC engine have odd weights, and to determine that a correctable 2-bit error exists when the upper index portions of the syndromes are one of predetermined even weight patterns.