ECC Decoder Memory Circuit With Per-Line Error History
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Solution Overview
Problem
As memory capacity increases, it becomes increasingly difficult to fabricate memory chips without defective memory cells, and existing methods like using redundant memory cells or error correction codes (ECC) are inadequate for efficient error correction during data transmission.
Innovation Solution
Incorporating an ECC decoder circuit and error storage circuit in the memory system to detect and store error histories, allowing for synchronized data and parity reception, and using ECC decoder circuits to correct errors and store error histories for each data line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory capacity is increased, then storage capability is improved, but the likelihood of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by performing error detection and correction before data is permanently lost or corrupted. The ECC decoder circuit continuously monitors incoming data through parity checks and corrects errors in real-time during data transmission, preventing defective cells from compromising overall system reliability.
Solution Approach 2:
The patent implements feedback mechanisms through parity bits and error correction codes that continuously monitor data integrity. The ECC decoder receives feedback about data errors through parity validation and automatically corrects detected errors, creating a closed-loop system that maintains reliability despite increased memory capacity.
2Reliability
If error correction code circuit is used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction function into distinct modular components: data receiving circuits, parity receiving circuits, and ECC decoder circuits. Each component handles specific aspects of error correction independently, making the overall system more manageable and maintainable despite the added complexity.
Solution Approach 2:
The ECC decoder circuit serves multiple functions simultaneously: it decodes error correction codes, validates parity bits, detects errors, and corrects defective memory cells. This multi-functionality reduces the need for separate dedicated circuits for each error handling task, thereby managing complexity while maintaining comprehensive error correction capability.
3Reliability
If redundant memory cells are used for repair, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the error correction function from the physical memory cell structure and implements it through separate ECC decoder circuits and parity validation logic. This separation allows standard memory cells to be used without requiring ultra-high manufacturing precision, as error correction is handled by dedicated correction circuits rather than relying on perfect fabrication.
Data Source
AI summary
A memory may include a plurality of data terminals, a plurality of data receiving circuits configured to receive data and a parity through the plurality of data terminals, an error correction code (ECC) decoder circuit configured to detect errors in the data and the parity using the data and the parity, and an error storage circuit configured to store a history of the errors detected by the ECC decoder circuit.