ECC Memory Word Layout for Reduced Flag-Bit Overhead
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Solution Overview
Problem
Conventional non-volatile memory devices with error correction code (ECC) function face challenges in miniaturization due to the occupation of additional area by flag bits, and turning off ECC for some words poses management and access issues.
Innovation Solution
A memory device with an ECC circuit that generates parity bits and flags to determine the ECC operation state based on parity bits and flags, allowing for reduced flag bits and improved reliability, enabling miniaturization and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flag bits are used to indicate ECC function state, then reliability is improved, but area is increased
Solution Approach 1:
The patent combines the ECC state indication function with existing memory structure elements. The flag bits are integrated into the memory word structure alongside data and parity bits, merging multiple functions into a unified storage unit. This eliminates the need for separate dedicated flag storage areas, thereby reducing overall device area while maintaining ECC reliability.
Solution Approach 2:
The memory word structure is designed to serve multiple purposes: storing data, storing parity bits for ECC, and indicating ECC state through flag bits within the same structure. This multi-functionality reduces the need for separate dedicated structures for each function, thereby reducing total area while maintaining all required functions including ECC reliability.
2Loss of energy
If ECC is turned off for certain words, then power consumption is reduced, but management complexity is increased
Solution Approach 1:
The patent divides the memory into individual memory words, each with its own flag bits indicating ECC state. This segmentation allows independent control of ECC for each word, enabling selective power consumption optimization without requiring complex global management. The controller can process each word independently based on its flag status, reducing overall management complexity.
Solution Approach 2:
Each memory word contains embedded flag bits that automatically indicate its ECC state. The controller simply reads these flag bits to determine whether to apply ECC processing, eliminating the need for complex external management or additional control signals. This self-service mechanism reduces power consumption selectively while keeping management simple.
Data Source
AI summary
A memory device including a memory array, an ECC circuit, and a memory controller is provided. The memory array is configured to store a memory word. The memory word includes a data, at least one parity bit and a flag. The ECC circuit is configured to generate the at least one parity bit of the data, and detect and correct an error of the data read out from the memory array based on the at least one parity bit of the read data. The memory controller is coupled to the memory array. The memory controller is configured to perform a read operation to read the memory word from the memory array, and perform a program operation to program the memory word into the memory array. The memory controller is configured to determine whether the ECC circuit is enabled during the read operation or the program operation to be performed on the memory word according to the memory word. The memory word is configured to indicate a predetermined state selected from at least two states of the ECC circuit.