Error Correction Code Memory Invalid Word Testing
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Solution Overview
Problem
Error-correction code memories in electronic devices face challenges in effectively testing and validating their error correction and detection capabilities due to the lack of intentionally invalid data for testing purposes.
Innovation Solution
Intentionally writing invalid words with single or multiple bits into error-correction code memories, which are then locked in read-only mode, allowing for the testing of error correction and detection circuits by simulating errors and verifying correction and detection operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error-correction code memory is implemented in electronic devices, then data integrity and reliability are improved, but the ability to test and validate error correction capabilities is worsened due to lack of intentionally invalid data for testing
Solution Approach 1:
The patent applies preliminary action by pre-loading intentionally invalid test words into the error-correction code memory during manufacturing or initialization. These test words with known error patterns (single-bit, double-bit, or multi-bit errors) are written into specific memory locations before the memory is deployed for normal operation. This allows the error correction circuit to be validated without requiring external testing equipment or complex test sequences, thus resolving the contradiction between maintaining data integrity and enabling easy testing.
2Difficulty of detecting and measuring
If conventional memory testing methods are used, then testing can be performed, but the error correction and detection capabilities cannot be thoroughly validated without intentionally invalid data
Solution Approach 1:
The patent converts the harmful effect of data corruption into a beneficial testing mechanism by intentionally creating invalid test words with specific error patterns. Instead of treating errors as unwanted defects to be eliminated, the invention embraces them as useful test cases. The error correction circuit is designed to recognize and correct these intentional errors, thereby validating its functionality. This approach transforms the problem of data invalidity into a solution for comprehensive error detection and correction testing.
3Ease of operation
If test data is written into memory, then error correction circuits can be tested, but the memory locations become occupied and may not be available for normal data storage
Solution Approach 1:
The patent applies local quality by designating specific memory locations for test words while preserving other locations for normal data storage. The error correction memory is divided into functional zones: test word locations containing intentionally invalid data for validation purposes, and data storage locations for normal operation. This spatial differentiation allows both testing and storage functions to coexist without interfering with each other, resolving the contradiction between ease of testing and available storage capacity.
Data Source
AI summary
An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.