Memory Page ECC Variation for Floating Gate Coupling
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Solution Overview
Problem
In non-volatile semiconductor memory devices, floating gate to floating gate coupling leads to erroneous data readings due to shifts in apparent charge, particularly affecting multi-state devices with narrower threshold voltage ranges, which can result in memory cells being shifted from allowed to forbidden ranges, compromising data integrity.
Innovation Solution
The technology optimizes data storage by designing rows with greater spacing and/or line width to minimize floating-gate to floating-gate coupling, using the reduced ECC requirements in more reliable pages to store block level information, thereby enhancing data integrity and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed with higher charge levels to increase storage capacity, then data density is improved, but floating gate coupling effects increase causing threshold voltage shifts and read errors
Solution Approach 1:
The memory array is divided into multiple independently controllable word lines. By selectively programming only the target word line while keeping adjacent word lines at read voltage, the patent segments the programming operation to minimize coupling effects from adjacent cells, thereby maintaining data integrity while achieving high charge levels.
Solution Approach 2:
Different voltage conditions are applied to different regions of the memory array during programming. The target word line receives program voltage while adjacent word lines receive read voltage, creating localized programming conditions that reduce coupling effects. This local differentiation allows high charge levels in target cells without compromising neighboring cells.
2Area of stationary object
If rows are spaced closer together to increase array density, then device area is reduced, but floating gate coupling between adjacent rows increases causing threshold voltage shifts
Solution Approach 1:
The patent employs dynamic voltage control where adjacent word lines are switched between read voltage and program voltage depending on the operation phase. During programming of a specific word line, adjacent lines are held at read voltage to minimize coupling, then switched to program voltage when their turn comes. This dynamic approach allows close spacing while maintaining threshold voltage stability.
3Quantity of substance
If multi-state memory cells are used to increase storage capacity, then data density is improved, but the narrower threshold voltage ranges make cells more susceptible to coupling-induced shifts into forbidden ranges
Solution Approach 1:
The patent applies preliminary verification after programming each word line to ensure threshold voltages are within allowed ranges before proceeding to the next programming operation. This preliminary check catches any cells that may have been shifted into forbidden ranges due to coupling effects, allowing for corrective action before subsequent programming operations that could exacerbate the problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data reliability by reducing the impact of floating-gate coupling, allowing for more efficient use of overhead space and improved error correction capabilities, leading to increased data integrity and reduced errors in memory devices.
Implementation Method 1
Shifts in the apparent charge stored on a floating gate or other charge region can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates.
Data Source
AI summary
A data structure for a memory device is provided. The device includes an array having a plurality of rows of storage elements divided into logical units composed of a plurality of data structures. The data structure includes a data sector including user data and user attribute data. The user attribute data includes error correction coding (ECC) for the user data. The user attribute data includes information for other sectors in the logical unit. The data sector is provided in one of the plurality of rows having a higher degree of data integrity than others of said plurality of rows.