ECC Memory Parity Circuit for Shorter Write Cycles
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Solution Overview
Problem
Semiconductor memory devices with error checking and correcting (ECC) circuits face longer write cycle times due to the need to regenerate parity bits during data writing, which lengthens the computation time required for error correction.
Innovation Solution
A semiconductor memory device with a parity generation circuit, memory cell array, syndrome generation circuit, and parity correction circuit that generates parity bits for input data and part of the read data, allowing for parallel syndrome and parity generation during writing, reducing the write cycle time and memory capacity required for parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are regenerated during data writing for error correction, then error detection accuracy is improved, but write cycle time increases
Solution Approach 1:
The patent pre-calculates and stores syndrome bits along with parity bits in the memory cell array before actual data writing occurs. During the write operation, these pre-computed syndrome bits are directly retrieved and used for error correction, eliminating the need to perform time-consuming syndrome calculations during the write cycle. This preliminary preparation of correction data resolves the contradiction by maintaining high error detection accuracy while significantly reducing write cycle time.
2Quantity of substance
If more data bits are assigned to one parity bit, then the number of required parity bits decreases, but memory capacity required for storing parity bits increases
Solution Approach 1:
The patent merges the storage of parity bits and syndrome bits into a unified memory structure within the memory cell array. By combining these two types of data that are both used for error correction, the system achieves more efficient space utilization. The syndrome bits, which are computational byproducts of the parity check matrix, are stored alongside the parity bits they correspond to, reducing redundant storage requirements and optimizing the overall memory capacity usage for error correction functionality.
Data Source
AI summary
A semiconductor memory device includes a parity generation circuit which generates a parity bit corresponding to a first number of data bits, a memory cell array including memory cells, and having first and second areas, the first area storing data, the second area storing the parity bit, a syndrome generation circuit which generates a syndrome bit for correcting an error in read data which are read from the first area, has the first number of data bits and corresponds to the parity bit read from the second area, based on the parity bit and the read data, and a parity correction circuit which corrects the parity bit generated by the parity generation circuit. The parity generation circuit generates the parity bit for data which includes input data and a part of the read data.