ECC Memory Array Layout With Distributed Parity Bits
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Solution Overview
Problem
Conventional semiconductor storage devices with Error Checking and Correcting (ECC) circuits face challenges in managing increased chip area and ECC process performance due to the provision of parity cells, leading to reliability and yield issues as miniaturization advances.
Innovation Solution
A semiconductor storage device design that includes a memory array with normal and parity arrays, ECC circuit sections, and data latches arranged to minimize layout area, using multiplexers to optimize ECC process bits and parity bits distribution, allowing for efficient error detection and correction while reducing chip area and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the bit width of the ECC process is increased to reduce the proportion of check bits, then the proportion of check bits decreases, but the number of wiring lines between memory array and ECC process circuit increases, leading to an increase in chip area
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture by placing the ECC process circuit on a different layer (third wiring layer) above the memory array (first wiring layer) and data latches (second wiring layer). This vertical stacking reduces the horizontal footprint and wiring congestion on individual layers while maintaining all necessary connections through vertical vias, effectively resolving the contradiction between processing width and chip area.
Solution Approach 2:
The patent implements a nested hierarchical structure where the ECC process circuit is positioned above the data latches, which in turn are positioned above the memory array. This nested arrangement allows multiple functional blocks to occupy different vertical levels within the same horizontal footprint, maximizing space utilization and reducing the overall chip area while supporting wide-bit ECC processing.
2Device complexity
If the syndrome generating circuit, syndrome decoding circuit, and error correcting circuit are provided in common to each block and arranged at separate positions, then the wiring region increases, leading to an increase in layout area, and also the wiring length increases, leading to an increase in process time
Solution Approach 1:
The patent merges the syndrome generating circuit, syndrome decoding circuit, and error correcting circuit into a single integrated ECC process circuit block. This consolidation eliminates the need for separate circuit blocks and their associated wiring, significantly reducing the total wiring region and layout area. The unified structure processes multiple data bits simultaneously through a single standardized interface, resolving the contradiction between circuit flexibility and area efficiency.
3Area of stationary object
If the wiring line between memory array and ECC process circuit increases, then the wiring length between bits is likely to be unbalanced, leading to a decrease in the performance of the ECC process
Solution Approach 1:
The patent applies local quality optimization by carefully designing the wiring layout within the ECC process circuit to ensure balanced signal paths. The circuit architecture is configured so that all data bit inputs originate from the same physical location (data latches), and all outputs converge to a single point (input/output section). This localized signal routing ensures uniform wiring lengths and balanced timing characteristics, maintaining high ECC process performance while utilizing the compact stacked architecture.
Data Source
AI summary
Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform.