ECC Memory Architecture for Fast Partial Writes and Bus Error Correction
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Solution Overview
Problem
Conventional error correction codes for memories in system-on-chips (SoCs) face issues such as high timing overhead, inefficient handling of partial writes, and neglect of crosstalk on long buses, which impact system performance and reliability, especially in mission-critical applications.
Innovation Solution
The implementation of an electronic circuit with a memory circuit, address and data buffers, a control circuit, and error correcting code (ECC) mechanisms that include a multiplexer, comparator, and mixer circuit to manage partial writes, generate parity bits, and bypass data from a write buffer during reads, utilizing Hsiao codes for low overhead and high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC schemes based on Hamming codes are used, then error detection and correction capability is provided, but timing overhead increases and system operating frequency decreases
Solution Approach 1:
The memory system is segmented into multiple banks, allowing parallel error correction operations to be performed simultaneously across different banks. This segmentation enables the system to maintain error correction capability while reducing the effective timing overhead by distributing the correction workload across multiple independent units operating in parallel.
Solution Approach 2:
Error correction codes are pre-calculated and stored in lookup tables during design time. During operation, the system performs preliminary actions by pre-charging sense amplifiers and pre-positioning correction data in buffers before actual memory access occurs. This eliminates the need for complex real-time error calculation, significantly reducing timing overhead while maintaining reliability.
2Loss of time
If pipelining is used to reduce timing overhead, then timing overhead decreases, but throughput decreases due to CPU having to defer memory transactions
Solution Approach 1:
An intermediary buffer structure is introduced between the CPU and the pipelined error correction system. This buffer acts as a mediator that absorbs the pipeline latency, allowing the CPU to continue issuing memory transactions without waiting for error correction to complete. The buffer holds intermediate results while the pipeline processes, maintaining both low timing overhead and high throughput by decoupling CPU operation from error correction timing.
3Difficulty of detecting and measuring
If conventional testing methods using ATPG or BIST techniques are used, then gate and cell level faults are detected, but crosstalk on long buses is ignored
Solution Approach 1:
The error correction system is designed with multi-functionality to handle multiple types of faults simultaneously. The same ECC circuitry that corrects bit errors also detects bus crosstalk errors through syndrome analysis. The system universally handles both traditional gate-level faults and electromagnetic crosstalk effects, providing comprehensive protection without requiring separate dedicated testing mechanisms for each fault type.
4Ease of operation
If partial writes are handled using conventional methods, then memory write operations are performed, but throughput is impacted due to inefficient handling
Solution Approach 1:
The system performs partial error correction by applying ECC only to the specific portion of data being written or read, rather than processing the entire memory word. For partial writes, the system calculates ECC only for the modified bytes and merges them with pre-calculated ECC for unchanged bytes. This selective approach maintains full partial write capability while significantly improving throughput by reducing the amount of error correction computation required for each operation.
Data Source
AI summary
An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.