ECC Memory Read Path With Concurrent Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in achieving fast data access while maintaining error correction reliability, as internal error detection and correction operations introduce latency in read and write operations.
Innovation Solution
The memory device performs concurrent internal error detection and correction operations while bypassing the internal error detection and correction process during access operations, allowing for immediate data output and storing error correction information generated by the host device during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If internal error detection and correction operations are performed during data access, then data reliability is improved, but access latency increases
Solution Approach 1:
The patent performs error detection and correction operations in advance during write operations, storing correction information with the data. This preliminary action allows read operations to skip time-consuming error correction processing while maintaining data reliability, as the correction information is already available from the preliminary write-phase processing.
Solution Approach 2:
The patent separates error correction operations from data access operations by performing them at different times. Error detection and correction are segmented into the write path (where they occur before data is stored), while read operations can proceed without waiting for error correction, thus resolving the latency-reliability contradiction through temporal segmentation of functions.
2Reliability
If error correction processing is performed during read operations, then data integrity is improved, but read speed decreases
Solution Approach 1:
Error correction processing is performed preliminarily during write operations rather than during read operations. The correction information is generated and stored with the data in advance, enabling fast reads without sacrificing data integrity, as the correction work was already done during the write phase.
Solution Approach 2:
The patent creates a copy of the correction information during write operations and stores it alongside the data. This copying approach allows the original data to be retrieved quickly during reads without requiring time-consuming error correction processing, as the correction data is already available as a pre-prepared copy.
Data Source
AI summary
Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.