ECC Memory Scrubbing for MRAM Data Retention Under Disturbance
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Solution Overview
Problem
Non-volatile memory technologies like MRAM face challenges with read and write performance due to read-disturb errors and hard breakdown at high voltage operations, requiring advanced error correction methods to ensure long-term data retention, especially at higher temperatures, while also being sensitive to environmental disturbances and power consumption.
Innovation Solution
The implementation of an error correcting memory system that includes a data scrubbing circuit electrically coupled to both data and ECC memories, capable of correcting errors using a longer code word length than normal access, and featuring an environmental disturbance sensor to generate scrub data commands based on detected conditions, such as temperature and magnetic fields, to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher voltage operation is used to improve read and write performance, then speed is improved, but reliability deteriorates due to read-disturb errors and hard breakdown
Solution Approach 1:
The patent applies preliminary action by performing data scrubbing operations before errors accumulate to critical levels. The system proactively reads and corrects data in the background during idle periods or low-activity states, preventing read-disturb errors and hard breakdown from compromising data integrity during high-performance operations.
Solution Approach 2:
The patent introduces an intermediary error correction code (ECC) mechanism that mediates between the high-voltage memory operations and data integrity requirements. The ECC system acts as a buffer, detecting and correcting errors introduced by high-voltage read and write operations without requiring reduction of operational voltage.
2Reliability
If advanced error correction methods are implemented to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction functionality into modular components: ECC encoding circuits, ECC decoding circuits, and data scrubbing controllers. Each component handles specific aspects of error correction independently, allowing for easier design, fabrication, and maintenance while achieving comprehensive data protection.
Solution Approach 2:
The patent implements self-service through automatic data scrubbing operations that run in the background without requiring external intervention. The scrubbing controller autonomously monitors memory status, initiates correction operations when needed, and manages ECC code generation and application, reducing the need for complex external error management systems.
3Reliability
If larger ECC code word length is used to improve error correction efficiency, then reliability is improved, but area overhead increases
Solution Approach 1:
The patent applies partial action by implementing data scrubbing at strategically selected intervals rather than continuously. The system performs background scrubbing operations during idle periods or low-activity states, applying error correction to only the portions of data most susceptible to errors based on operational patterns, thereby reducing overall area overhead while maintaining effective error protection.
4Reliability
If data scrubbing operations are performed continuously to maintain data integrity, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by performing data scrubbing operations at predetermined intervals rather than continuously. The scrubbing controller is configured to initiate correction operations based on time-based schedules or event-driven triggers, allowing the memory system to maintain data integrity while consuming power only when correction operations are actually needed.
Data Source
AI summary
Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.