ECC Memory Parity Layout for Single-Line Error Correction
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Solution Overview
Problem
Conventional ECC memory systems, such as those using Hamming codes, incur a size and test time penalty due to the difference in stress patterns between data bits and parity bits, which is undesirable in components with small form factors or area resources.
Innovation Solution
A new ECC memory system that calculates parity bits using functions ensuring P1=P2=P3=P4=1, allowing data and parity bits to be accessed using a single data line, thereby simplifying the parity operation and reducing the surface area required for testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC memory systems use Hamming codes with separate data lines for parity bits, then error correction capability is maintained, but device area and test time increase
Solution Approach 1:
The patent merges the access paths for data bits and parity bits by calculating parity bits such that P1=P2=P3=P4=1, allowing both data and parity bits to be accessed through a single shared data line. This eliminates the need for separate parity data lines, reducing device area and test time while maintaining error correction capability through the same ECC mechanism.
Solution Approach 2:
The single data line is designed to serve multiple functions: it can access both data bits and parity bits depending on the operation mode. The ECC memory system uses a unified access interface that can handle different bit types without requiring dedicated lines, thereby reducing overall device complexity and area.
2Ease of operation
If conventional ECC memory systems use separate data lines for data and parity bits, then access operations are straightforward, but test time and device complexity increase
Solution Approach 1:
By merging the access paths for data and parity bits into a single data line, the patent reduces the number of access operations required during testing. The unified access interface allows the same line to be used for both data and parity bit access, halving the test time compared to systems that require separate lines for each bit type.
3Reliability
If ECC memory uses conventional Hamming codes with multiple data lines, then error detection and correction are reliable, but the system occupies more area resources
Solution Approach 1:
The patent combines multiple data lines into a single shared data line by designing parity bit calculation functions that ensure P1=P2=P3=P4=1. This merging reduces the number of physical data lines from multiple separate lines to one unified line, decreasing device complexity while preserving the error detection and correction functionality through the same ECC code structure.
Solution Approach 2:
The patent changes the parameters of the parity bit calculation by imposing the constraint P1=P2=P3=P4=1, which fundamentally alters how parity bits are generated and accessed. This parameter change enables the use of a single data line for both data and parity bits, reducing device complexity without compromising error correction reliability.
Data Source
AI summary
Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data. A minimum distance of three in the disclosed ECC is maintained to make certain that a single bit is corrected on the read data to retrieve the originally stored memory data.