ECC and Memory Tag Cache for DRAM Bandwidth Optimization
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Solution Overview
Problem
In traditional DRAM designs, especially for low-cost solutions like mobile devices, the in-line ECC and memory tagging mechanisms lead to increased memory read operations, degrading data transfer rates and bandwidth due to the need for separate ECC and memory tag reads, resulting in slower performance.
Innovation Solution
Implementing an ECC cache and a memory tag cache, or a combined cache, to store error correction and memory tag data in a high-speed cache, reducing latency by allowing a single cache read to provide data for multiple requests and utilizing spatial and temporal locality to optimize data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If in-line ECC and memory tagging are implemented in DRAM, then data security and error correction are improved, but memory read operations increase and bandwidth degrades
Solution Approach 1:
The patent extracts ECC and MTE data from the main DRAM storage and places them in a separate high-speed cache memory. This separation allows ECC/MTE verification to occur independently from data access operations, eliminating the need for additional DRAM reads and preserving both security functionality and bandwidth performance.
Solution Approach 2:
The patent introduces a high-speed cache memory as an intermediary layer between the processor and DRAM. This cache stores ECC and MTE data alongside or separately from main data, acting as a mediator that provides fast access to verification data without requiring slow DRAM accesses, thus maintaining both reliability and productivity.
2Measurement precision
If separate ECC and memory tag reads are performed for every memory request, then data verification accuracy is improved, but latency increases
Solution Approach 1:
The patent performs preliminary action by pre-loading ECC and MTE data into the high-speed cache memory before they are needed for verification. The cache is populated in advance through cache lines that contain multiple ECC/MTE entries, so when a memory request arrives, the verification data is already available in fast memory, eliminating verification latency.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the cache memory continuously populated with ECC and MTE data. Instead of performing discrete read operations for each verification need, the system maintains a continuous state where verification data is readily available, eliminating idle time and ensuring uninterrupted verification operations.
3Reliability
If multiple memory read operations are performed to retrieve ECC and MTE data, then data integrity checking is improved, but data transfer rate decreases
Solution Approach 1:
The patent merges the storage of ECC and MTE data with the data they protect by organizing cache lines to contain both data and its associated verification information. This combining allows the system to retrieve both data and verification data in a single cache access operation, maintaining data integrity checking while maximizing data transfer rate by eliminating additional read operations.
Data Source
AI summary
A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.