In-line ECC Logic Memory Testing with Bypassed Error Correction
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Solution Overview
Problem
Conventional methods for testing error correction code (ECC) logic in memory systems are inadequate, leading to limited detection and correction of defects, which can result in corrupted data or failure to detect errors, thereby compromising the quality of shipped products.
Innovation Solution
A three-pass testing method that bypasses ECC logic during initial manufacturing tests, followed by enabling ECC logic with complex patterns generated by a linear feedback shift register to thoroughly test and repair ECC logic, and finally integrating ECC logic with built-in self-test (BIST) for in-system testing, ensuring enhanced memory reliability and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic is enabled during memory testing, then error detection and correction capability is improved, but test complexity and time increase
Solution Approach 1:
The testing process is divided into multiple passes: first passing tests memory without ECC to identify and repair defective cells, then subsequent passes enable ECC logic to verify correction effectiveness and test ECC functionality itself. This segmentation allows comprehensive testing while managing complexity through staged execution.
Solution Approach 2:
Before enabling ECC logic for testing, the method first performs preliminary memory testing with ECC bypassed to identify and repair defective cells. This preliminary action ensures that when ECC is subsequently enabled, the memory is in an optimized state, reducing the burden on ECC logic and simplifying the overall test process.
2Productivity
If ECC logic is bypassed during testing, then test time is reduced, but defect detection capability is limited
Solution Approach 1:
The test process is segmented into phases: initial fast testing with ECC bypassed to quickly identify obvious defects, followed by phases with ECC enabled to detect and correct errors. This segmentation maintains high productivity in early stages while ensuring comprehensive defect detection in subsequent stages.
Solution Approach 2:
The testing process continues iteratively with multiple passes, where each pass builds upon the previous one. Even after initial fast testing, the process continues with ECC-enabled testing to ensure complete defect detection and verification, maintaining continuous improvement in detection capability without permanently sacrificing speed.
3Reliability
If comprehensive memory testing with ECC enabled is performed, then product quality is improved, but manufacturing cost increases
Solution Approach 1:
The method applies partial ECC testing in initial passes (with ECC bypassed) and excessive ECC testing in subsequent passes (with ECC enabled). This combination ensures high product quality through thorough testing while managing manufacturing costs by using less resource-intensive methods where sufficient and more intensive methods where necessary.
Solution Approach 2:
The process discards test patterns and results from passes with ECC bypassed, then recovers and utilizes ECC logic in subsequent passes to verify corrections and detect additional defects. This selective use of testing resources optimizes the balance between quality assurance and manufacturing cost.
Data Source
AI summary
Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.