Embedded Memory ECC Logic Testing via Signal Switching
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Solution Overview
Problem
The integration of ECC logic into embedded memories complicates testing due to increased logical complexity and area requirements, leading to challenges in testing embedded ECC logic using traditional ATPG methods, which can result in area bloat and increased test time.
Innovation Solution
A double-staged memory testing procedure is employed, where a first test bypasses the ECC functionality to detect hard errors, followed by a second test that enables ECC functionality to test the ECC logic, using switching devices to select input signals and simulate errors for thorough ECC logic testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC logic is integrated into embedded memory, then soft error rate is reduced and memory reliability is improved, but testing complexity and difficulty increase significantly
Solution Approach 1:
The testing process is divided into two distinct stages: a first test that bypasses ECC functionality to detect hard errors in the memory array, and a second test that enables ECC functionality to specifically test the ECC logic. This segmentation allows each test to focus on specific components without interference, resolving the testing difficulty while maintaining reliability improvements.
Solution Approach 2:
Switching devices are introduced as intermediaries to control the flow of test signals and select whether ECC functionality is enabled or bypassed during testing. These switching devices mediate between the test apparatus and the memory-ECC system, enabling flexible test configuration without permanently altering the integrated structure, thus reducing testing difficulty while preserving reliability benefits.
2Ease of operation
If traditional ATPG methods are used to test externally attached ECC logic, then testing is straightforward, but memory area and cycle time are significantly increased
Solution Approach 1:
The ECC logic is merged with the embedded memory array into a single integrated structure, eliminating the need for separate externally attached ECC logic. This integration reduces the total memory area while maintaining ECC functionality. The switching devices enable the integrated structure to be tested effectively by controlling signal flow, thus achieving both area reduction and testing ease.
3Ease of manufacture
If ECC logic is externally attached to embedded memory, then ECC functionality is added straightforwardly, but cycle time and memory area are significantly impacted
Solution Approach 1:
The ECC logic is merged with the embedded memory array into a single integrated structure, eliminating the need for separate externally attached ECC logic. This integration reduces the total memory area while maintaining ECC functionality. The switching devices enable the integrated structure to be tested effectively by controlling signal flow, thus achieving both area reduction and testing ease.
Solution Approach 2:
The system dynamically switches between different operational modes during testing: a first mode where ECC functionality is bypassed for hard error detection, and a second mode where ECC functionality is enabled for ECC logic testing. This dynamic switching capability allows the integrated structure to adapt to different test requirements without permanently compromising performance, thus reducing cycle time while maintaining ease of manufacture.
Data Source
AI summary
A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.