ECC Memory Timing via Segmented HREADY Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In pipeline communication systems, particularly those using the Advanced Microcontroller Bus Architecture (AHB) protocol, the detection of ECC errors introduces a significant delay in memory access time due to the dependency of the HREADY signal on ECC or parity check logic, affecting system performance.
Innovation Solution
The introduction of two additional control signals, HREADY_OUT and HREADY_OUT_TO_SLAVE, which are generated independently of the error check, allowing for improved timing and arbitration logic to manage access phases and prevent premature accesses, thereby reducing critical path dependencies on memory access and ECC checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC or parity check logic is used to detect errors in memory data, then data reliability is improved, but memory access time increases significantly due to HREADY signal dependency
Solution Approach 1:
The HREADY signal generation is segmented into two independent paths: one path handles memory access timing without ECC dependency, while another path handles ECC error detection. This segmentation allows the memory access phase to proceed independently of the error checking phase, eliminating the timing bottleneck caused by ECC dependency on HREADY signal.
Solution Approach 2:
The slave device performs ECC or parity checks on memory data in advance, before the master device needs to access the data. By completing error detection beforehand and preparing the corrected data, the system eliminates waiting time during memory access operations, as the data is already validated and ready for transfer.
2Reliability
If HREADY signal is overwritten by ECC check logic to force HREADY low when errors are found, then error detection capability is improved, but system productivity decreases due to access delays
Solution Approach 1:
An intermediary mechanism is introduced where the slave device internally manages ECC error detection and data correction without forcing HREADY low. The slave uses internal flags and control logic to handle error responses, allowing the HREADY signal to maintain its timing function while error detection proceeds independently through separate control paths.
3Ease of operation
If slave uses HREADY signal to detect when to process new access, then protocol simplicity is maintained, but timing precision deteriorates due to ECC check interference
Solution Approach 1:
The HREADY signal functionality is segmented into two distinct signals: HREADY_OUT for master communication (timing indication) and HREADY_OUT_TO_SLAVE for slave-to-slave communication (access permission). This segmentation allows each signal to perform its specific function without interference from ECC check logic, maintaining both protocol simplicity and timing precision.
Solution Approach 2:
A copy of the HREADY signal functionality is created as HREADY_OUT_TO_SLAVE, which replicates the timing indication function for slave devices without being affected by ECC check interference. This copying approach allows the original HREADY signal to maintain protocol simplicity while the copy provides accurate timing information for slave access operations.
Data Source
AI summary
A pipeline communication system includes a master and a plurality of slaves configured to communicate with each other. Each of the plurality of slaves includes a memory, and is configured to generate a first ready signal and a second ready signal. The first ready signal is configured to be provided only to the master and the second ready signal is configured to be provided only to each of the plurality of slaves. The second ready signal is generated independent of the error check in each of the plurality of slaves.