ECC Memory Write Pipelining for Faster Masked Operations
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Solution Overview
Problem
Semiconductor memory devices face increased susceptibility to soft errors due to reduced feature sizes and voltage levels, leading to decreased charge storage margins and errors from alpha particle interactions and weak memory cells, which can result in random single bit errors, and error correction codes, while improving data integrity, also increase memory operation time, reducing performance.
Innovation Solution
The implementation of a memory system with a write driver, data sense amplifier, error control code circuit, and control circuit that enables pipelining of consecutive write mask operations, allowing for concurrent execution of operations and reduced execution time by starting the second write mask operation before the first completes, thereby minimizing the column-to-column delay and enhancing memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used to correct data errors in memory cells, then data integrity is improved, but the time required for memory operations increases, reducing memory performance
Solution Approach 1:
The patent applies preliminary action by pre-charging local input-output lines before read operations and pre-computing ECC codes before write operations. This preparation work is done in advance so that when actual read/write operations occur, the time penalty is minimized. Specifically, the system pre-charges bit lines and pre-computes syndrome codes, allowing ECC operations to proceed more efficiently without significantly impacting overall memory performance.
Solution Approach 2:
The patent implements continuity of useful action by overlapping ECC operations with memory operations. While read operations are occurring, ECC syndrome computation is performed in parallel. Similarly, while write operations are occurring, ECC code generation continues uninterrupted. This overlapping of operations ensures that the useful work of error correction continues without idle time, maintaining high productivity while ensuring data integrity.
2Area of stationary object
If feature sizes of semiconductor memory are reduced to produce smaller memory components, then memory capacity per area is increased, but the margin of error for detecting data state decreases, making memory more prone to soft errors
Solution Approach 1:
The patent applies preliminary action by implementing variable refresh timing based on predicted error susceptibility. Memory cells are identified as high-risk or low-risk based on their error history and characteristics, and refresh operations are scheduled accordingly. High-risk cells receive more frequent refreshes before they can develop errors, while low-risk cells receive standard refreshes. This preliminary identification and differential scheduling maintains reliability without requiring uniform high-frequency refresh across all cells.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the refresh interval parameter for different memory cells based on their error susceptibility. Instead of using a fixed refresh period for all cells, the system varies the refresh timing parameter - applying shorter intervals to cells showing signs of degradation or higher error rates, and longer intervals to stable cells. This adaptive parameter adjustment maintains data integrity while optimizing refresh efficiency.
Data Source
AI summary
Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.