Parallel ECC Merge Circuits for Masked Write Data Integrity
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Solution Overview
Problem
In integrated circuits with data mask options, existing error correction code (ECC) methods face inefficiencies due to sequential operations that increase processing time and overhead, especially when correcting errors in masked data portions during write operations.
Innovation Solution
The implementation of parallel ECC circuits that selectively correct data errors and generate parity codes independently for masked and unmasked data portions, allowing simultaneous error correction and parity code generation, reducing the need for sequential operations and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential ECC decode and encode operations are used during write operations with data mask, then error correction accuracy is improved, but processing time and overhead increase
Solution Approach 1:
The patent divides the data word into multiple portions (e.g., first portion and second portion) and processes them through separate parallel ECC circuits simultaneously. The first ECC circuit decodes and corrects errors in the first portion while the second ECC circuit encodes parity for the second portion, eliminating the need for sequential operations and reducing processing time while maintaining error correction accuracy.
2Reliability
If separate parity codes are generated for each maskable portion of the data word, then error correction capability is improved, but device complexity and overhead increase
Solution Approach 1:
The patent implements separate ECC circuits for different portions of the data word, with each circuit handling specific segments independently. This segmentation allows parallel processing of different data portions while maintaining dedicated error correction capability for each segment, improving reliability without requiring a complete redesign of the ECC system.
Solution Approach 2:
The patent uses a unified parity code structure that serves multiple functions: it provides error detection and correction for the entire data word while also enabling independent error correction for masked portions. The same ECC encoding/decoding logic is applied across different data portions, reducing device complexity through code reuse rather than requiring entirely separate correction mechanisms.
3Reliability
If data mask option is implemented during write operations, then data integrity is improved, but processing overhead increases due to dependency on corrected old data
Solution Approach 1:
The patent performs preliminary error correction on masked data portions before the final data merge operation. By using parallel ECC circuits that simultaneously correct errors in old data and generate parity for new data, the system prepares corrected data portions in advance, eliminating the need for sequential correction and reducing processing overhead while maintaining data integrity.
Solution Approach 2:
The patent introduces an intermediary merged data word that combines corrected old data portions with new data portions before final parity generation. This intermediary structure allows the system to handle data mask operations efficiently by providing a clear separation between data that needs correction and data that needs encoding, reducing the complexity of dependency management while maintaining data integrity.
Data Source
AI summary
One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.