ECC Decoder Logic That Confines Miscorrections to One Data Block
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Solution Overview
Problem
Memory chips with decreasing feature sizes exhibit higher bit error rates, leading to faulty error correction where additional errors are introduced during internal correction attempts, causing the memory controller's ECC algorithm to fail in correcting cache lines.
Innovation Solution
The ECC algorithm on memory chips is designed to constrain additional errors within the same block as the original errors in the raw data portion or within the check bits, ensuring that the memory controller's ECC algorithm can still correct errors by keeping the code word within its error correction threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chip feature sizes are reduced to increase storage capacity, then storage density is improved, but bit error rate increases leading to faulty error correction
Solution Approach 1:
The raw data bits are divided into multiple blocks, and the ECC decoder constrains additional errors to occur within the same block as the original errors. This segmentation approach allows the memory controller's ECC algorithm to correct errors more effectively by limiting the spread of additional errors, thus resolving the contradiction between increased storage capacity and maintained reliability at smaller feature sizes.
2Reliability
If the memory chip ECC algorithm attempts to correct errors internally, then error correction capability is improved, but additional errors are introduced causing correction failure
Solution Approach 1:
The ECC decoder implements local quality control by constraining additional errors to occur within the same block as the original errors, rather than distributing them randomly across the entire code word. This localized error confinement maintains the overall error correction capability while reducing the harmful effect of additional errors on the memory controller's correction process.
3Reliability
If the memory controller's ECC algorithm corrects errors, then data integrity is maintained, but performance overhead increases
Solution Approach 1:
The memory chip ECC algorithm performs partial error correction by handling only the original errors and confining additional errors to the same block, rather than attempting to correct all errors. This partial action reduces the correction burden on the memory controller, thereby maintaining data integrity while reducing performance overhead.
Data Source
AI summary
An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.