On-Chip ECC Miscorrection Detection for Memory Test Yield
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Solution Overview
Problem
Memory devices with on-chip ECC schemes face issues in accurately distinguishing between correctable errors and miscorrections during testing, leading to false fail determinations and unnecessary repair operations, which reduce yield.
Innovation Solution
Incorporating a miscorrection detection circuit to identify and mask test results when an error correction operation is performed on data without errors, preventing miscorrections and ensuring accurate test outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip ECC scheme is implemented to correct errors in memory cells, then reliability of data storage is improved, but false fail determinations occur during testing due to miscorrection of error-free data
Solution Approach 1:
A miscorrection detection circuit is introduced as an intermediary component between the error correction circuit and the test output circuit. This circuit monitors the error correction process and generates a miscorrection detection signal when error-free data is incorrectly flagged. The signal masks the test result to prevent false fail determinations, thereby resolving the contradiction between maintaining data reliability through ECC and ensuring accurate test measurements.
2Reliability
If error correction operations are performed on all read data, then data integrity is improved, but unnecessary repair operations are triggered during testing, reducing manufacturing yield
Solution Approach 1:
The miscorrection detection circuit provides feedback by monitoring the error correction process and comparing the error location signal with the actual data state. When miscorrection is detected (error-free data incorrectly identified as erroneous), the circuit generates a mask signal that feeds back to the test output circuit. This feedback mechanism prevents unnecessary repair operations by distinguishing between actual errors and miscorrections, thereby maintaining data integrity while improving manufacturing yield.
3Measurement precision
If miscorrection detection circuit is added to prevent false fail determinations, then test accuracy is improved, but device complexity increases
Solution Approach 1:
The miscorrection detection circuit is merged with the existing error correction circuit architecture. The detection circuit utilizes the same error location signal already generated by the ECC circuit for correction purposes. By sharing the error location signal generation logic and using the existing data paths, the patent minimizes additional circuit complexity while achieving accurate miscorrection detection. The detection function is integrated into the flow rather than being a completely separate system.
Data Source
AI summary
A memory device includes a normal cell region and a parity cell region; an error correction circuit configured to perform an error correction operation on read data output from the normal cell region based on read parity bits output from the parity cell region to generate error-corrected data; a miscorrection detection circuit configured to detect whether the error correction operation is performed on the read data not containing an error bit to generate a miscorrection detection signal; and a test output circuit configured to generate, in a test mode, a test result signal corresponding to the error-corrected data while masking the test result signal according to the miscorrection detection signal.