Memory ECC Distribution Across Blocks, Pages, and Chips
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Solution Overview
Problem
Existing error correction codes in computer memory devices are less effective in correcting errors when they occur in physically grouped memory cells, as they are typically designed to handle errors within a single block or page, leading to inefficiencies in reliability.
Innovation Solution
The solution involves mixing data and error correction code (ECC) portions across multiple block storage locations within a page and between pages, as well as between memory chips, to spread out the data and ECC over a larger physical area, thereby increasing the likelihood of error correction and compensating for block and page-based weaknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If error correction code is stored within a single block or page, then the storage structure is simple, but the ability to correct physically grouped errors deteriorates
Solution Approach 1:
The patent divides the error correction code into multiple segments and distributes them across different block storage locations, pages, and memory chips. This segmentation allows the ECC to cover a broader physical area, improving its ability to correct physically grouped errors while maintaining manageable complexity through systematic distribution patterns.
Solution Approach 2:
The patent extends the error correction code distribution from a single-block dimension to multi-dimensional distribution across blocks, pages, and chips. This dimensional expansion enables the ECC to protect against errors that are grouped in any of these physical dimensions, significantly improving reliability without proportionally increasing complexity.
2Speed
If data and ECC are concentrated in one block, then the write operation is fast, but the reliability against physically grouped errors deteriorates
Solution Approach 1:
The patent segments both data and error correction code across multiple block storage locations within a page and between pages. This segmentation distributes the write operations across multiple locations, maintaining high speed through parallel operations while improving reliability by spreading the ECC coverage over a larger physical area to catch grouped errors.
Solution Approach 2:
The patent combines data portions and ECC portions from multiple blocks into a unified error correction scheme. By merging the protection coverage across blocks, pages, and chips, the system achieves both fast operation through efficient encoding/decoding and improved reliability through broader error coverage.
3Productivity
If ECC covers only a single block, then the processing overhead is low, but the error correction capability for grouped errors deteriorates
Solution Approach 1:
The patent extends ECC coverage from single-block to multi-dimensional coverage across blocks, pages, and chips. This dimensional expansion improves error correction capability for grouped errors while maintaining processing efficiency through systematic distribution patterns that enable efficient encoding and decoding operations across the extended coverage area.
Solution Approach 2:
The patent creates a universal error correction scheme that functions across multiple levels of the memory hierarchy (blocks, pages, chips). This multi-functional ECC system can correct errors at any level of the hierarchy, improving reliability without proportionally increasing processing overhead through efficient use of the same correction mechanisms across different scopes.
Data Source
AI summary
Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.