Dynamic ECC Mode Switching for DQ Line Sparing
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Solution Overview
Problem
Current memory systems face significant challenges in addressing uncorrectable errors (UEs) caused by data signal (DQ) failures, which lead to server downtime and performance impacts due to the limitations of existing sparing techniques, such as bank sparing and row sparing, which either reduce memory capacity or performance.
Innovation Solution
A system that dynamically switches error correction code (ECC) mode on-the-fly to spare a failing DQ line by remapping ECC bits to the failed DQ bits, allowing for on-the-fly ECC downgrading and repurposing of ECC bits as data bits, thereby maintaining system reliability and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bank sparing is used to spare a failed bitline, then sparing coverage for DQ failure is provided, but memory capacity is significantly reduced and performance is impacted
Solution Approach 1:
The invention segments the memory system into functional components (data bits and ECC bits) that can be dynamically reassigned. When a DQ failure occurs, the system segments the ECC function from its dedicated bits and reallocates those bits for data storage, while using remaining ECC capacity for error correction. This segmentation allows partial sparing without complete bank offline, resolving the contradiction between providing sparing coverage and maintaining memory capacity.
Solution Approach 2:
The invention implements dynamic ECC mode switching that allows the system to transition between different ECC configurations at runtime. The error manager can dynamically adjust the number of ECC bits used for correction versus data storage based on the specific failure mode detected. This dynamic adaptation enables the system to provide DQ sparing coverage while minimizing capacity loss, as opposed to static bank sparing that permanently offline entire banks.
2Reliability
If bank sparing is used to spare a failed bitline, then sparing coverage for DQ failure is provided, but system performance is significantly impacted
Solution Approach 1:
The invention implements dynamic ECC mode switching that allows the system to transition between different ECC configurations at runtime. The error manager can dynamically adjust the number of ECC bits used for correction versus data storage based on the specific failure mode detected. This dynamic adaptation enables the system to provide DQ sparing coverage while minimizing capacity loss, as opposed to static bank sparing that permanently offline entire banks.
Solution Approach 2:
The invention changes the operational parameters of the ECC system by allowing runtime adjustment of ECC mode (e.g., switching between 128-bit, 96-bit, or 64-bit ECC modes). When a DQ failure is detected, the system changes the ECC parameter configuration to use fewer ECC bits for correction, freeing up bits for data storage and maintaining performance. This parameter flexibility resolves the contradiction between reliability and performance.
3Reliability
If row sparing is used, then defective rows can be replaced, but DQ failure coverage is not provided
Solution Approach 1:
The invention makes the ECC system universal by enabling it to handle multiple types of failures through the same mechanism. The error manager can detect various failure modes (row defects, DQ failures, column defects) and dynamically switch ECC modes to address the specific failure type. This multi-functionality allows the system to provide both row sparing coverage and DQ failure coverage through a unified approach, resolving the contradiction between row defect coverage and DQ failure coverage.
4Quantity of substance
If ECC mode is downgraded, then more bits are available for data storage, but error correction coverage is reduced
Solution Approach 1:
The invention changes the operational parameters of the ECC system by allowing runtime adjustment of ECC mode (e.g., switching between 128-bit, 96-bit, or 64-bit ECC modes). When a DQ failure is detected, the system changes the ECC parameter configuration to use fewer ECC bits for correction, freeing up bits for data storage and maintaining performance. This parameter flexibility resolves the contradiction between reliability and performance.
Data Source
AI summary
A system provides DO-level sparing to spare a fault of a data signal (DQ) line of a memory bus. The data bus has multiple data dynamic random access memory (DRAM) devices and at least one error correction code (ECC) DRAM device coupled to it. An error manager can be in the memory controller or in a platform error controller. The error manager to detect a DQ failure and dynamically switches ECC mode on the fly. The error manager can map out data bits of the DQ and remap ECC bits of the at least one ECC DRAM device to the mapped out data bits of the DQ.