ECC Circuit with Parallel Error Detection for Faster Memory Reads
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Solution Overview
Problem
Conventional multi-bit error correction circuits in semiconductor memory devices are inefficient, requiring more processing time and resulting in slower data read times due to their design based on a maximum number of correctable error bits, leading to prolonged error correction cycles.
Innovation Solution
An error correction circuit with multiple error position detectors operating in parallel and a determiner to determine the error type, allowing for selective and efficient error position calculations based on the number of detected error bits, reducing the overall data read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-bit error correction circuits are designed based on maximum number of correctable error bits, then error correction capability is ensured, but processing time increases and data read speed decreases
Solution Approach 1:
The error correction circuit is segmented into multiple error position detectors, each specialized for detecting a specific number of error bits (e.g., one detector for 1-bit errors, another for 2-bit errors, etc.). Each detector operates independently and in parallel, processing only the error type it is designed for. This segmentation allows the system to quickly identify the actual error type and apply the appropriate correction without performing full multi-bit error correction procedures for all cases, thereby maintaining error correction capability while significantly reducing average processing time and improving data read speed.
2Reliability
If conventional error correction circuits perform full error correction cycles for all cases, then all error types can be corrected, but error correction cycle time is prolonged
Solution Approach 1:
The error correction circuit dynamically adapts its operation based on the detected error type. Instead of always performing the complete multi-bit error correction cycle, the system uses multiple error position detectors to first identify the actual number of error bits present. Once the error type is identified (e.g., 1-bit, 2-bit, or 3-bit error), the circuit dynamically selects and executes only the necessary correction procedure for that specific error type. This dynamic adaptation ensures that all error types can be corrected while minimizing the error correction cycle time by avoiding unnecessary processing steps for lighter error cases.
3Speed
If parallel error position detectors are used to reduce processing time, then data read speed increases, but device complexity increases
Solution Approach 1:
The circuit is divided into multiple specialized error position detectors, each handling a specific error type (1-bit detector, 2-bit detector, 3-bit detector, etc.). Each detector is relatively simple in structure, designed to handle only its specific error type efficiently. This segmentation approach allows parallel operation for speed while keeping individual detector complexity low. The main controller integrates these detectors and coordinates their output, managing the overall system complexity through a structured approach that balances parallel processing capability with manageable circuit design.
Data Source
AI summary
An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. The semiconductor memory device includes the error correction circuit, an error checking and correcting (ECC) encoder generating syndrome data based on information data and generating the coded data by combining the syndrome data with information data, and a memory core storing the coded data. Multi-bit ECC performance is maintained and ECC for a predetermined (1 or 2) or less number of error bits is quickly performed.