ECC Parity Embedding in DRAM Mask Bits
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Solution Overview
Problem
Dynamic random access memory (DRAM) scaling increases the number of weak retention cells, leading to additional refresh cycles and random bit refresh errors, while existing error correction codes (ECCs) degrade memory performance and do not adequately protect the memory link, resulting in insufficient reliability for high-performance systems.
Innovation Solution
Embedding ECC parity bits within unused data mask bits during normal write and read operations, and in data bytes during mask write operations, using a memory controller with an ECC encoder/decoder to generate and transfer these bits, ensuring error correction without bandwidth loss or memory interface changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC codes are applied to correct random bit errors in the memory cell array, then memory reliability is improved, but read access time increases due to ECC decoding overhead
Solution Approach 1:
The patent extracts the ECC parity bits from the data mask bits during mask write operations, allowing the ECC to be transmitted separately without interfering with the data mask functionality. This separation enables the memory controller to perform ECC decoding independently without blocking the data mask bit from serving its original purpose of controlling data write operations.
Solution Approach 2:
The patent implements dynamic multiplexing where the data mask bits serve dual purposes: during normal write operations, they control data write enablement; during mask write operations, they carry ECC parity bits. This dynamic reassignment allows the same physical signal to serve different functions at different times, eliminating the need for additional dedicated ECC transmission lines.
2Quantity of substance
If DRAM scaling increases the total number of bits per chip, then storage capacity is improved, but the number of weak retention cells increases leading to more refresh cycles and random bit errors
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors the data mask bits during mask write operations to detect and correct errors in the memory cell array. The ECC parity bits provide real-time feedback about the integrity of stored data, allowing the system to detect and correct random bit errors that arise from DRAM scaling and refresh cycles.
3Reliability
If additional ECC parity bits are added to protect memory link errors, then memory reliability is improved, but memory system cost and power consumption increase
Solution Approach 1:
The patent makes the data mask bits universal by enabling them to serve multiple functions: during normal write operations, they control data write enablement; during mask write operations, they carry ECC parity bits. This multi-functionality eliminates the need for separate dedicated ECC transmission lines, thereby reducing the overall memory system cost and power consumption while still providing comprehensive error protection.
Data Source
AI summary
A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.