ECC Parity Bit Layout for Adjacent Multi-Bit Error Correction
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Solution Overview
Problem
As memory bit cells in integrated circuits (ICs) become smaller and denser, the likelihood of Single Event Upsets (SEUs) impacting multiple memory bit cells increases, and existing Error-Correcting Codes (ECCs) struggle to effectively correct errors without compromising memory bandwidth.
Innovation Solution
The implementation of an encoder and decoder circuit block that generates and orders parity bits to detect and correct single, double, and triple bit errors, including adjacent errors, independent of the number of memory banks, using Hamming Code-like structures with additional parity bits for enhanced error detection and correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional parity bits are added to correct larger amounts of data corruption, then error correction capability is improved, but memory bandwidth deteriorates
Solution Approach 1:
The error correction capability is segmented into multiple levels: single bit error correction, double bit error detection, and adjacent double bit error correction. This segmentation allows the system to provide comprehensive error protection without requiring a single massive parity bit structure that would consume excessive bandwidth.
Solution Approach 2:
The encoder circuit block is designed to generate multiple types of parity bits (first set for single bit and double bit error handling, second set for adjacent double bit error handling) that serve multiple error correction functions simultaneously, making the system universally applicable to various error scenarios without requiring separate dedicated parity structures for each error type.
2Quantity of substance
If memory bit cells are made smaller and denser, then storage capacity is improved, but susceptibility to Single Event Upsets deteriorates
Solution Approach 1:
The patent implements error correction capabilities in advance by encoding data with multiple sets of parity bits before storage. The encoder circuit block generates comprehensive error detection and correction codes that cushion against future Single Event Upset errors, allowing the system to recover from errors without data loss even as bit cell density increases and SEU susceptibility rises.
Data Source
AI summary
An apparatus includes an encoder circuit block configured to receive input data. The encoder circuit block is configured to generate a plurality of parity bits from the input data and order the input data and the plurality of parity bits to generate encoded data. The encoder circuit block is configured to generate each of the plurality of parity bits based upon selected bits of the input data and orders the input data and the plurality of parity bits so that a decoder circuit block configured to decode the encoded data is able to perform operations including, at least in part, detecting a no bit error, detecting and correcting a single bit error, detecting a double bit error, detecting and correcting an adjacent double bit error, and detecting an adjacent triple bit error. The operations are independent of a number of memory banks used to store the encoded data. The decoder circuit block may also correct an adjacent triple bit error.