Parity Check Matrix Sub-Matrix Design for ECC Calculation Delay
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Solution Overview
Problem
Semiconductor memory devices face delays in calculating syndrome and parity data for error correction codes, particularly due to complex configurations in parity check matrices, which affect processing efficiency.
Innovation Solution
The semiconductor memory device employs a simplified parity check matrix configuration with sub matrices including identity and alpha matrices, where each sub matrix has a specific diagonal arrangement, reducing calculation skew and delay by matching high-level value elements across rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional parity check matrix configuration is used for ECC encoding, then error correction capability is maintained, but calculation delay increases and processing efficiency deteriorates
Solution Approach 1:
The parity check matrix is segmented into multiple sub-matrices, where each sub-matrix corresponds to specific data symbols. This segmentation allows the ECC engine to process different portions of data in parallel, reducing overall calculation delay while maintaining the error correction capability of the complete matrix structure.
Solution Approach 2:
The patent modifies the structural parameters of the parity check matrix by arranging sub-matrices with specific patterns of identity matrices and zero matrices. This parameter optimization enables more efficient calculation pathways without compromising the mathematical properties required for error correction, thereby improving processing efficiency.
2Reliability
If a complex parity check matrix configuration is used, then error correction capability is maintained, but device complexity increases
Solution Approach 1:
By dividing the parity check matrix into standardized sub-matrices with repeating patterns, the patent reduces configuration complexity. Each sub-matrix follows a template structure that is easier to implement and verify compared to a fully custom matrix configuration, while maintaining equivalent error correction reliability.
Solution Approach 2:
The patent employs homogeneous sub-matrices with identical or similar structures throughout the parity check matrix. This uniformity simplifies the overall configuration, reduces implementation complexity, and allows for standardized processing logic while preserving the mathematical properties needed for reliable error correction.
3Manufacturing precision
If detailed sub-matrix arrangements are implemented, then calculation precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent optimizes manufacturing precision by carefully selecting and positioning specific matrix elements (identity matrices and zero matrices) within each sub-matrix. These parameter optimizations enable precise calculation while the repeating patterns across sub-matrices simplify the manufacturing process through standardization.
Solution Approach 2:
The patent uses copied templates for sub-matrices throughout the parity check matrix. Instead of manually configuring each matrix element, standardized sub-matrix templates are replicated and positioned systematically, which maintains calculation precision while significantly reducing manufacturing complexity and the potential for errors.
Data Source
AI summary
A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.