Memory Control Circuit ECC Parity Integration

Solution Overview

Problem

Existing memory systems face challenges in efficiently utilizing memory capacity while maintaining high reliability, as additional error protection data increases the resource consumption and complexity of memory circuits.

Innovation Solution

The integration of error correction code (ECC) and parity in memory control circuits allows for increased memory utilization by repurposing some bits in supplemental blocks for metadata, while maintaining error protection through ECC symbols and parity bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error protection data bits are increased to provide higher level error protection, then reliability is improved, but device complexity and resource consumption increase

Engineering Contradiction:

Improveerror protection levelVSAvoidmemory circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines ECC protection and parity protection into a unified error protection scheme. The memory controller integrates both ECC circuits and parity circuits to work together, allowing supplemental blocks to serve dual purposes for error protection while reducing overall system complexity compared to implementing separate full ECC protection for all data blocks.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The supplemental blocks are designed to serve multiple functions: they provide ECC protection for data blocks, contain parity bits for additional error detection, and can be repurposed to store metadata. This multi-functionality increases memory utilization while maintaining comprehensive error protection across the memory system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If error protection data bits are increased to provide higher level error protection, then reliability is improved, but memory capacity utilization deteriorates

Engineering Contradiction:

Improveerror protection levelVSAvoidmemory capacity utilization

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The supplemental blocks are designed to serve multiple functions: they provide ECC protection for data blocks, contain parity bits for additional error detection, and can be repurposed to store metadata. This multi-functionality increases memory utilization while maintaining comprehensive error protection across the memory system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of applying full ECC protection to all data blocks, the patent applies ECC protection selectively to certain data blocks while using parity bits for other blocks. This partial application of error protection mechanisms reduces the total number of protection bits required while maintaining adequate error protection levels across the entire memory capacity.

Inventive Principle:

Principle #16Partial or excessive action

3Quantity of substance

If bits in supplemental blocks are repurposed for metadata, then memory utilization is improved, but error protection capability deteriorates

Engineering Contradiction:

Improvememory utilizationVSAvoiderror protection capability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent segments the error protection mechanism into two parts: ECC protection for data blocks and parity protection for supplemental blocks. This segmentation allows flexible allocation where ECC-protected data blocks can have their supplemental blocks repurposed for metadata while maintaining error protection through the parity bits stored in those same supplemental blocks.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The supplemental blocks are designed to serve multiple functions: they provide ECC protection for data blocks, contain parity bits for additional error detection, and can be repurposed to store metadata. This multi-functionality increases memory utilization while maintaining comprehensive error protection across the memory system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12204410B2Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization

Publication Date: 2025.01.21 AMPERE COMPUTING LLC

AI summary

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.