Memory Sub-System Hybrid ECC and Parity Decoding for Error Recovery
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Solution Overview
Problem
Conventional memory sub-systems, such as RAID configurations, are limited in correcting errors across multiple memory components, failing to recover data if more than one component in RAID 5 or two components in RAID 6 configurations experience errors, and lack integration with error correction codes for enhanced reliability without adding redundant data or components.
Innovation Solution
Implementing hybrid iterative error correcting code decoding operations and redundancy error correction decoding operations, where a first level of error correction code decoding corrects data using error correction codes and a second level uses parity data for redundancy correction, with iterative processes based on a threshold condition to reconstruct data, thereby enhancing error correction capabilities without additional redundant components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RAID configurations are used for error correction, then data recovery is possible for single component failures, but data cannot be recovered if more than one component experiences errors
Solution Approach 1:
The patent combines error correction code decoding and redundancy decoding into a unified hybrid decoding system. The controller integrates both ECC and RAID redundancy mechanisms, allowing them to work together in an iterative manner to correct errors that would exceed the capability of either system alone, thereby improving reliability without adding physical redundant components
Solution Approach 2:
The patent implements dynamic decoding selection where the controller adaptively chooses between conventional decoding, hybrid iterative decoding, and different iteration counts based on the detected error patterns and threshold conditions. This dynamic approach allows the system to optimize performance and reliability for different error scenarios without requiring additional hardware
2Reliability
If error correction codes are applied to correct data, then bit errors can be corrected, but the system cannot handle cases where too many bits are corrupted beyond correction capability
Solution Approach 1:
The patent applies error correction code decoding as a preliminary step before redundancy decoding. By first attempting to correct errors using ECC, the system reduces the error burden on subsequent redundancy decoding operations, enabling the hybrid system to handle higher error rates than either method could achieve independently
3Reliability
If redundancy decoding operations are performed on all data, then data integrity is maintained, but processing time and computational resources increase
Solution Approach 1:
The patent implements threshold-based selective redundancy decoding where decoding operations are performed iteratively only when error thresholds are exceeded. The system monitors error conditions and activates full hybrid decoding only when necessary, rather than applying it universally to all data, thereby reducing average processing time while maintaining data integrity when needed
Solution Approach 2:
The patent uses iterative decoding with configurable iteration counts that can be adjusted based on error conditions. The decoding process performs multiple passes with increasing sophistication only as needed, allowing the system to balance processing speed and reliability by adapting the intensity and duration of decoding operations to the actual error state
Data Source
AI summary
Data stored on each of a set of memory components can be read. Corresponding data stored on a number of the set of memory components that cannot be decoded using an error correction code decoding operation can be identified. A determination can be made whether the number of the set of memory components that include the corresponding data that cannot be decoded from the ECC decoding operation satisfies a threshold condition. Responsive to determining that the number of the set of memory components that include the corresponding data that cannot be decoded from the second ECC decoding operation satisfies the threshold condition, a processing device, can perform a redundancy error correction decoding operation to correct the data stored on each of the set of memory components.